tests/amdgpu: add draw test for gfx10

Signed-off-by: Flora Cui <flora.cui@amd.com>

3 files changed, 451 insertions, 138 deletions

diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index 068840c9..9f4453db 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -285,8 +285,8 @@ extern CU_TestInfo cp_dma_tests[];
 void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip_type);
 void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type);
 void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring,
-			     int hang);
-void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring);
+			     int version, int hang);
+void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring, int version);
 
 /**
  * Initialize security test suite
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 8afd05c1..43b80c88 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -292,6 +292,8 @@ CU_TestInfo basic_tests[] = {
 #define PKT3_SET_SH_REG                        0x76
 #define		PACKET3_SET_SH_REG_START			0x00002c00
 
+#define PKT3_SET_SH_REG_INDEX			0x9B
+
 #define	PACKET3_DISPATCH_DIRECT				0x15
 #define PACKET3_EVENT_WRITE				0x46
 #define PACKET3_ACQUIRE_MEM				0x58
@@ -390,6 +392,32 @@ static const uint32_t preamblecache_gfx9[] = {
 	0xc0017900, 0x24b, 0x0
 };
 
+static const uint32_t preamblecache_gfx10[] = {
+	0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
+	0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
+	0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
+	0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
+	0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
+	0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0,
+	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
+	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
+	0xc0046900, 0x310, 0, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0xe, 0x20,
+	0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
+	0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x6, 0x0,
+	0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
+	0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+	0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
+	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
+	0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
+	0xc0016900, 0x2db, 0, 0xc0016900, 0x1d4, 0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, 0xc0016900, 0xe, 0x2,
+	0xc0016900, 0x206, 0x300, 0xc0016900, 0x212, 0x200, 0xc0017900, 0x7b, 0x20, 0xc0017a00, 0x20000243, 0x0,
+	0xc0017900, 0x249, 0, 0xc0017900, 0x24a, 0, 0xc0017900, 0x24b, 0, 0xc0017900, 0x259, 0xffffffff,
+	0xc0017900, 0x25f, 0, 0xc0017900, 0x260, 0, 0xc0017900, 0x262, 0,
+	0xc0017600, 0x45, 0x0, 0xc0017600, 0x6, 0x0,
+	0xc0067600, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+	0xc0067600, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
+};
+
 enum ps_type {
 	PS_CONST,
 	PS_TEX,
@@ -442,6 +470,39 @@ static const uint32_t ps_const_context_reg_gfx9[][2] = {
     {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 }
 };
 
+static const uint32_t ps_const_shader_gfx10[] = {
+    0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
+    0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000,
+    0xF8001C0F, 0x00000100, 0xBF810000
+};
+
+static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6;
+
+static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = {
+    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000000 },
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000100 },
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000300 },
+     { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
+     { 0xD7690000, 0x00020300, 0xD7690001, 0x00020702, 0xF8001C0F, 0x00000100 },
+     { 0xD7680000, 0x00020300, 0xD7680001, 0x00020702, 0xF8001C0F, 0x00000100 },
+     { 0xD76A0000, 0x00020300, 0xD76A0001, 0x00020702, 0xF8001C0F, 0x00000100 },
+     { 0xD76B0000, 0x00020300, 0xD76B0001, 0x00020702, 0xF8001C0F, 0x00000100 },
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100 }
+    }
+};
+
+static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = {
+    0x00000004
+};
+
+static const uint32_t ps_num_sh_registers_gfx10 = 2;
+
+static const uint32_t ps_const_sh_registers_gfx10[][2] = {
+    {0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 },
+    {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
+};
+
 static const uint32_t ps_tex_shader_gfx9[] = {
     0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD4180000,
     0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00,
@@ -485,6 +546,34 @@ static const uint32_t ps_tex_context_reg_gfx9[][2] = {
     {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004  }
 };
 
+static const uint32_t ps_tex_shader_gfx10[] = {
+    0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000,
+    0xC80C0100, 0xC8090001, 0xC80D0101, 0xF0800F0A,
+    0x00400402, 0x00000003, 0xBEFE040E, 0xBF8C0F70,
+    0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000,
+    0xF8001C0F, 0x00000100, 0xBF810000
+};
+
+static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = {
+    0x0000000C
+};
+
+static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6;
+
+static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = {
+    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000004 },
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000504 },
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000704 },
+     { 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
+     { 0xD7690000, 0x00020B04, 0xD7690001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+     { 0xD7680000, 0x00020B04, 0xD7680001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+     { 0xD76A0000, 0x00020B04, 0xD76A0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+     { 0xD76B0000, 0x00020B04, 0xD76B0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x07060504 }
+    }
+};
+
 static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
     0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100,
     0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206,
@@ -496,6 +585,17 @@ static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
     0xC400020F, 0x05060403, 0xBF810000
 };
 
+static const uint32_t vs_RectPosTexFast_shader_gfx10[] = {
+    0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206,
+    0x7C040080, 0x060000F3, 0xD5010001, 0x01AA0200,
+    0x7E060203, 0xD5010002, 0x01AA0404, 0x7E080207,
+    0x7C040080, 0xD5010000, 0x01A80101, 0xD5010001,
+    0x01AA0601, 0x7E060208, 0x7E0A02F2, 0xD5010002,
+    0x01A80902, 0xD5010004, 0x01AA0805, 0x7E0C0209,
+    0xF80008CF, 0x05030100, 0xF800020F, 0x05060402,
+    0xBF810000
+};
+
 static const uint32_t cached_cmd_gfx9[] = {
 	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
 	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
@@ -507,6 +607,17 @@ static const uint32_t cached_cmd_gfx9[] = {
 	0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
 };
 
+static const uint32_t cached_cmd_gfx10[] = {
+	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
+	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
+	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
+	0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x18,
+	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
+	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
+	0xc0026900, 0x292, 0x20, 0x6020000,
+	0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
+};
+
 unsigned int memcpy_ps_hang[] = {
         0xFFFFFFFF, 0xBEFE0A7E, 0xBEFC0304, 0xC0C20100,
         0xC0800300, 0xC8080000, 0xC80C0100, 0xC8090001,
@@ -3004,7 +3115,7 @@ static int amdgpu_draw_load_ps_shader_hang_slow(uint32_t *ptr, int family)
 	return 0;
 }
 
-static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type)
+static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type, uint32_t version)
 {
 	int i;
 	uint32_t shader_offset= 256;
@@ -3016,18 +3127,34 @@ static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type)
 
 	switch (ps_type) {
 		case PS_CONST:
-			shader = ps_const_shader_gfx9;
-			shader_size = sizeof(ps_const_shader_gfx9);
-			patchinfo_code = (const uint32_t *)ps_const_shader_patchinfo_code_gfx9;
-			patchinfo_code_size = ps_const_shader_patchinfo_code_size_gfx9;
-			patchcode_offset = ps_const_shader_patchinfo_offset_gfx9;
+			if (version == 9) {
+				shader = ps_const_shader_gfx9;
+				shader_size = sizeof(ps_const_shader_gfx9);
+				patchinfo_code = (const uint32_t *)ps_const_shader_patchinfo_code_gfx9;
+				patchinfo_code_size = ps_const_shader_patchinfo_code_size_gfx9;
+				patchcode_offset = ps_const_shader_patchinfo_offset_gfx9;
+			} else if (version == 10){
+				shader = ps_const_shader_gfx10;
+				shader_size = sizeof(ps_const_shader_gfx10);
+				patchinfo_code = (const uint32_t *)ps_const_shader_patchinfo_code_gfx10;
+				patchinfo_code_size = ps_const_shader_patchinfo_code_size_gfx10;
+				patchcode_offset = ps_const_shader_patchinfo_offset_gfx10;
+			}
 			break;
 		case PS_TEX:
-			shader = ps_tex_shader_gfx9;
-			shader_size = sizeof(ps_tex_shader_gfx9);
-			patchinfo_code = (const uint32_t *)ps_tex_shader_patchinfo_code_gfx9;
-			patchinfo_code_size = ps_tex_shader_patchinfo_code_size_gfx9;
-			patchcode_offset = ps_tex_shader_patchinfo_offset_gfx9;
+			if (version == 9) {
+				shader = ps_tex_shader_gfx9;
+				shader_size = sizeof(ps_tex_shader_gfx9);
+				patchinfo_code = (const uint32_t *)ps_tex_shader_patchinfo_code_gfx9;
+				patchinfo_code_size = ps_tex_shader_patchinfo_code_size_gfx9;
+				patchcode_offset = ps_tex_shader_patchinfo_offset_gfx9;
+			} else if (version == 10) {
+				shader = ps_tex_shader_gfx10;
+				shader_size = sizeof(ps_tex_shader_gfx10);
+				patchinfo_code = (const uint32_t *)ps_tex_shader_patchinfo_code_gfx10;
+				patchinfo_code_size = ps_tex_shader_patchinfo_code_size_gfx10;
+				patchcode_offset = ps_tex_shader_patchinfo_offset_gfx10;
+			}
 			break;
 		case PS_HANG:
 			shader = memcpy_ps_hang;
@@ -3059,20 +3186,25 @@ static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type)
 }
 
 /* load RectPosTexFast_VS */
-static int amdgpu_draw_load_vs_shader(uint8_t *ptr)
+static int amdgpu_draw_load_vs_shader(uint8_t *ptr, uint32_t version)
 {
 	const uint32_t *shader;
 	uint32_t shader_size;
 
-	shader = vs_RectPosTexFast_shader_gfx9;
-	shader_size = sizeof(vs_RectPosTexFast_shader_gfx9);
+	if (version == 9) {
+		shader = vs_RectPosTexFast_shader_gfx9;
+		shader_size = sizeof(vs_RectPosTexFast_shader_gfx9);
+	} else if (version == 10) {
+		shader = vs_RectPosTexFast_shader_gfx10;
+		shader_size = sizeof(vs_RectPosTexFast_shader_gfx10);
+	}
 
 	memcpy(ptr, shader, shader_size);
 
 	return 0;
 }
 
-static int amdgpu_draw_init(uint32_t *ptr)
+static int amdgpu_draw_init(uint32_t *ptr, uint32_t version)
 {
 	int i = 0;
 	const uint32_t *preamblecache_ptr;
@@ -3083,8 +3215,13 @@ static int amdgpu_draw_init(uint32_t *ptr)
 	ptr[i++] = 0x80000000;
 	ptr[i++] = 0x80000000;
 
-	preamblecache_ptr = preamblecache_gfx9;
-	preamblecache_size = sizeof(preamblecache_gfx9);
+	if (version == 9) {
+		preamblecache_ptr = preamblecache_gfx9;
+		preamblecache_size = sizeof(preamblecache_gfx9);
+	} else if (version == 10) {
+		preamblecache_ptr = preamblecache_gfx10;
+		preamblecache_size = sizeof(preamblecache_gfx10);
+	}
 
 	memcpy(ptr + i, preamblecache_ptr, preamblecache_size);
 	return i + preamblecache_size/sizeof(uint32_t);
@@ -3092,41 +3229,95 @@ static int amdgpu_draw_init(uint32_t *ptr)
 
 static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr,
 							 uint64_t dst_addr,
+							 uint32_t version,
 							 int hang_slow)
 {
 	int i = 0;
 
 	/* setup color buffer */
-	/* offset   reg
-	   0xA318   CB_COLOR0_BASE
-	   0xA319   CB_COLOR0_BASE_EXT
-	   0xA31A   CB_COLOR0_ATTRIB2
-	   0xA31B   CB_COLOR0_VIEW
-	   0xA31C   CB_COLOR0_INFO
-	   0xA31D   CB_COLOR0_ATTRIB
-	   0xA31E   CB_COLOR0_DCC_CONTROL
-	   0xA31F   CB_COLOR0_CMASK
-	   0xA320   CB_COLOR0_CMASK_BASE_EXT
-	   0xA321   CB_COLOR0_FMASK
-	   0xA322   CB_COLOR0_FMASK_BASE_EXT
-	   0xA323   CB_COLOR0_CLEAR_WORD0
-	   0xA324   CB_COLOR0_CLEAR_WORD1
-	   0xA325   CB_COLOR0_DCC_BASE
-	   0xA326   CB_COLOR0_DCC_BASE_EXT */
-	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 15);
-	ptr[i++] = 0x318;
-	ptr[i++] = dst_addr >> 8;
-	ptr[i++] = dst_addr >> 40;
-	ptr[i++] = hang_slow ? 0x1ffc7ff : 0x7c01f;
-	ptr[i++] = 0;
-	ptr[i++] = 0x50438;
-	ptr[i++] = 0x10140000;
-	i += 9;
+	if (version == 9) {
+		/* offset   reg
+		   0xA318   CB_COLOR0_BASE
+		   0xA319   CB_COLOR0_BASE_EXT
+		   0xA31A   CB_COLOR0_ATTRIB2
+		   0xA31B   CB_COLOR0_VIEW
+		   0xA31C   CB_COLOR0_INFO
+		   0xA31D   CB_COLOR0_ATTRIB
+		   0xA31E   CB_COLOR0_DCC_CONTROL
+		   0xA31F   CB_COLOR0_CMASK
+		   0xA320   CB_COLOR0_CMASK_BASE_EXT
+		   0xA321   CB_COLOR0_FMASK
+		   0xA322   CB_COLOR0_FMASK_BASE_EXT
+		   0xA323   CB_COLOR0_CLEAR_WORD0
+		   0xA324   CB_COLOR0_CLEAR_WORD1
+		   0xA325   CB_COLOR0_DCC_BASE
+		   0xA326   CB_COLOR0_DCC_BASE_EXT */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 15);
+		ptr[i++] = 0x318;
+		ptr[i++] = dst_addr >> 8;
+		ptr[i++] = dst_addr >> 40;
+		ptr[i++] = hang_slow ? 0x3ffc7ff : 0x7c01f;
+		ptr[i++] = 0;
+		ptr[i++] = 0x50438;
+		ptr[i++] = 0x10140000;
+		i += 9;
+
+		/* mmCB_MRT0_EPITCH */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+		ptr[i++] = 0x1e8;
+		ptr[i++] = hang_slow ? 0xfff : 0x1f;
+	} else if (version == 10) {
+		/* 0xA318   CB_COLOR0_BASE
+		   0xA319   CB_COLOR0_PITCH
+		   0xA31A   CB_COLOR0_SLICE
+		   0xA31B   CB_COLOR0_VIEW
+		   0xA31C   CB_COLOR0_INFO
+		   0xA31D   CB_COLOR0_ATTRIB
+		   0xA31E   CB_COLOR0_DCC_CONTROL
+		   0xA31F   CB_COLOR0_CMASK
+		   0xA320   CB_COLOR0_CMASK_SLICE
+		   0xA321   CB_COLOR0_FMASK
+		   0xA322   CB_COLOR0_FMASK_SLICE
+		   0xA323   CB_COLOR0_CLEAR_WORD0
+		   0xA324   CB_COLOR0_CLEAR_WORD1
+		   0xA325   CB_COLOR0_DCC_BASE */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 14);
+		ptr[i++] = 0x318;
+		ptr[i++] = dst_addr >> 8;
+		i += 3;
+		ptr[i++] = 0x50438;
+		i += 9;
+
+		/* 0xA390   CB_COLOR0_BASE_EXT */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+		ptr[i++] = 0x390;
+		ptr[i++] = dst_addr >> 40;
+
+		/* 0xA398   CB_COLOR0_CMASK_BASE_EXT */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+		ptr[i++] = 0x398;
+		ptr[i++] = 0;
 
-	/* mmCB_MRT0_EPITCH */
-	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
-	ptr[i++] = 0x1e8;
-	ptr[i++] = hang_slow ? 0x7ff : 0x1f;
+		/* 0xA3A0   CB_COLOR0_FMASK_BASE_EXT */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+		ptr[i++] = 0x3a0;
+		ptr[i++] = 0;
+
+		/* 0xA3A8   CB_COLOR0_DCC_BASE_EXT */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+		ptr[i++] = 0x3a8;
+		ptr[i++] = 0;
+
+		/* 0xA3B0   CB_COLOR0_ATTRIB2 */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+		ptr[i++] = 0x3b0;
+		ptr[i++] = hang_slow ? 0x3ffc7ff : 0x7c01f;
+
+		/* 0xA3B8   CB_COLOR0_ATTRIB3 */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+		ptr[i++] = 0x3b8;
+		ptr[i++] = 0x9014000;
+	}
 
 	/* 0xA32B   CB_COLOR1_BASE */
 	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
@@ -3144,15 +3335,24 @@ static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr,
 	ptr[i++] = 9;
 
 	/* Setup depth buffer */
-	/* mmDB_Z_INFO */
-	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
-	ptr[i++] = 0xe;
-	i += 2;
+	if (version == 9) {
+		/* mmDB_Z_INFO */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
+		ptr[i++] = 0xe;
+		i += 2;
+	} else if (version == 10) {
+		/* mmDB_Z_INFO */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
+		ptr[i++] = 0x10;
+		i += 2;
+	}
 
 	return i;
 }
 
-static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr, int hang_slow)
+static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr,
+						     uint32_t version,
+						     int hang_slow)
 {
 	int i = 0;
 	const uint32_t *cached_cmd_ptr;
@@ -3168,7 +3368,10 @@ static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr, int hang_slo
 
 	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
 	ptr[i++] = 0xd7;
-	ptr[i++] = 1;
+	if (version == 9)
+		ptr[i++] = 1;
+	else if (version == 10)
+		ptr[i++] = 0;
 
 	/* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
 	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16);
@@ -3180,20 +3383,37 @@ static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr, int hang_slo
 	ptr[i++] = 0x2f5;
 	i += 2;
 
-	cached_cmd_ptr = cached_cmd_gfx9;
-	cached_cmd_size = sizeof(cached_cmd_gfx9);
+	if (version == 9) {
+		cached_cmd_ptr = cached_cmd_gfx9;
+		cached_cmd_size = sizeof(cached_cmd_gfx9);
+	} else if (version == 10) {
+		cached_cmd_ptr = cached_cmd_gfx10;
+		cached_cmd_size = sizeof(cached_cmd_gfx10);
+	}
 
 	memcpy(ptr + i, cached_cmd_ptr, cached_cmd_size);
 	if (hang_slow)
 		*(ptr + i + 12) = 0x8000800;
 	i += cached_cmd_size/sizeof(uint32_t);
 
+	if (version == 10) {
+		/* mmCB_RMI_GL2_CACHE_CONTROL */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+		ptr[i++] = 0x104;
+		ptr[i++] = 0x40aa0055;
+		/* mmDB_RMI_L2_CACHE_CONTROL */
+		ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+		ptr[i++] = 0x1f;
+		ptr[i++] = 0x2a0055;
+	}
+
 	return i;
 }
 
 static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr,
 						  int ps_type,
 						  uint64_t shader_addr,
+						  uint32_t version,
 						  int hang_slow)
 {
 	int i = 0;
@@ -3203,10 +3423,21 @@ static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr,
 	ptr[i++] = 0x207;
 	ptr[i++] = 0;
 
-	/* mmSPI_SHADER_PGM_RSRC3_VS */
-	ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
-	ptr[i++] = 0x46;
-	ptr[i++] = 0xffff;
+	if (version == 9) {
+		/* mmSPI_SHADER_PGM_RSRC3_VS */
+		ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
+		ptr[i++] = 0x46;
+		ptr[i++] = 0xffff;
+	} else if (version == 10) {
+		/* mmSPI_SHADER_PGM_RSRC3_VS */
+		ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1);
+		ptr[i++] = 0x30000046;
+		ptr[i++] = 0xffff;
+		/* mmSPI_SHADER_PGM_RSRC4_VS */
+		ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1);
+		ptr[i++] = 0x30000041;
+		ptr[i++] = 0xffff;
+	}
 
 	/* mmSPI_SHADER_PGM_LO_VS...mmSPI_SHADER_PGM_HI_VS */
 	ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
@@ -3217,7 +3448,10 @@ static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr,
 	/* mmSPI_SHADER_PGM_RSRC1_VS */
 	ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
 	ptr[i++] = 0x4a;
-	ptr[i++] = 0xc0081;
+	if (version == 9)
+		ptr[i++] = 0xc0081;
+	else if (version == 10)
+		ptr[i++] = 0xc0041;
 	/* mmSPI_SHADER_PGM_RSRC2_VS */
 	ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
 	ptr[i++] = 0x4b;
@@ -3258,7 +3492,8 @@ static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr,
 
 static int amdgpu_draw_ps_write2hw(uint32_t *ptr,
 				   int ps_type,
-				   uint64_t shader_addr)
+				   uint64_t shader_addr,
+				   uint32_t version)
 {
 	int i, j;
 	const uint32_t *sh_registers;
@@ -3266,9 +3501,14 @@ static int amdgpu_draw_ps_write2hw(uint32_t *ptr,
 	uint32_t num_sh_reg, num_context_reg;
 
 	if (ps_type == PS_CONST) {
-		sh_registers = (const uint32_t *)ps_const_sh_registers_gfx9;
+		if (version == 9) {
+			sh_registers = (const uint32_t *)ps_const_sh_registers_gfx9;
+			num_sh_reg = ps_num_sh_registers_gfx9;
+		} else if (version == 10) {
+			sh_registers = (const uint32_t *)ps_const_sh_registers_gfx10;
+			num_sh_reg = ps_num_sh_registers_gfx10;
+		}
 		context_registers = (const uint32_t *)ps_const_context_reg_gfx9;
-		num_sh_reg = ps_num_sh_registers_gfx9;
 		num_context_reg = ps_num_context_registers_gfx9;
 	} else if (ps_type == PS_TEX) {
 		sh_registers = (const uint32_t *)ps_tex_sh_registers_gfx9;
@@ -3279,15 +3519,35 @@ static int amdgpu_draw_ps_write2hw(uint32_t *ptr,
 
 	i = 0;
 
-	/* 0x2c07   SPI_SHADER_PGM_RSRC3_PS
-	   0x2c08   SPI_SHADER_PGM_LO_PS
-	   0x2c09   SPI_SHADER_PGM_HI_PS */
-	shader_addr += 256 * 9;
-	ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3);
-	ptr[i++] = 0x7;
-	ptr[i++] = 0xffff;
-	ptr[i++] = shader_addr >> 8;
-	ptr[i++] = shader_addr >> 40;
+	if (version == 9) {
+		/* 0x2c07   SPI_SHADER_PGM_RSRC3_PS
+		   0x2c08   SPI_SHADER_PGM_LO_PS
+		   0x2c09   SPI_SHADER_PGM_HI_PS */
+		/* multiplicator 9 is from  SPI_SHADER_COL_FORMAT */
+		shader_addr += 256 * 9;
+		ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3);
+		ptr[i++] = 0x7;
+		ptr[i++] = 0xffff;
+		ptr[i++] = shader_addr >> 8;
+		ptr[i++] = shader_addr >> 40;
+	} else if (version == 10) {
+		shader_addr += 256 * 9;
+		/* 0x2c08	 SPI_SHADER_PGM_LO_PS
+		     0x2c09	 SPI_SHADER_PGM_HI_PS */
+		ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
+		ptr[i++] = 0x8;
+		ptr[i++] = shader_addr >> 8;
+		ptr[i++] = shader_addr >> 40;
+
+		/* mmSPI_SHADER_PGM_RSRC3_PS */
+		ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1);
+		ptr[i++] = 0x30000007;
+		ptr[i++] = 0xffff;
+		/* mmSPI_SHADER_PGM_RSRC4_PS */
+		ptr[i++] = PACKET3(PKT3_SET_SH_REG_INDEX, 1);
+		ptr[i++] = 0x30000001;
+		ptr[i++] = 0xffff;
+	}
 
 	for (j = 0; j < num_sh_reg; j++) {
 		ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
@@ -3312,19 +3572,29 @@ static int amdgpu_draw_ps_write2hw(uint32_t *ptr,
 	return i;
 }
 
-static int amdgpu_draw_draw(uint32_t *ptr)
+static int amdgpu_draw_draw(uint32_t *ptr, uint32_t version)
 {
 	int i = 0;
 
-	/* mmIA_MULTI_VGT_PARAM */
-	ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
-	ptr[i++] = 0x40000258;
-	ptr[i++] = 0xd00ff;
-
-	/* mmVGT_PRIMITIVE_TYPE */
-	ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
-	ptr[i++] = 0x10000242;
-	ptr[i++] = 0x11;
+	if (version == 9) {
+		/* mmIA_MULTI_VGT_PARAM */
+		ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+		ptr[i++] = 0x40000258;
+		ptr[i++] = 0xd00ff;
+		/* mmVGT_PRIMITIVE_TYPE */
+		ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+		ptr[i++] = 0x10000242;
+		ptr[i++] = 0x11;
+	} else if (version == 10) {
+		/* mmGE_CNTL */
+		ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+		ptr[i++] = 0x25b;
+		ptr[i++] = 0xff;
+		/* mmVGT_PRIMITIVE_TYPE */
+		ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+		ptr[i++] = 0x242;
+		ptr[i++] = 0x11;
+	}
 
 	ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1);
 	ptr[i++] = 3;
@@ -3338,7 +3608,7 @@ void amdgpu_memset_draw(amdgpu_device_handle device_handle,
 			amdgpu_bo_handle bo_shader_vs,
 			uint64_t mc_address_shader_ps,
 			uint64_t mc_address_shader_vs,
-			uint32_t ring_id)
+			uint32_t ring_id, uint32_t version)
 {
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo_dst, bo_cmd, resources[4];
@@ -3372,15 +3642,16 @@ void amdgpu_memset_draw(amdgpu_device_handle device_handle,
 	CU_ASSERT_EQUAL(r, 0);
 
 	i = 0;
-	i += amdgpu_draw_init(ptr_cmd + i);
+	i += amdgpu_draw_init(ptr_cmd + i, version);
 
-	i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 0);
+	i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, version, 0);
 
-	i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 0);
+	i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, version, 0);
 
-	i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs, 0);
+	i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs,
+						    version, 0);
 
-	i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_ps);
+	i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_ps, version);
 
 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
 	ptr_cmd[i++] = 0xc;
@@ -3389,7 +3660,7 @@ void amdgpu_memset_draw(amdgpu_device_handle device_handle,
 	ptr_cmd[i++] = 0x33333333;
 	ptr_cmd[i++] = 0x33333333;
 
-	i += amdgpu_draw_draw(ptr_cmd + i);
+	i += amdgpu_draw_draw(ptr_cmd + i, version);
 
 	while (i & 7)
 		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
@@ -3447,7 +3718,7 @@ void amdgpu_memset_draw(amdgpu_device_handle device_handle,
 }
 
 static void amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
-				    uint32_t ring)
+				    uint32_t ring, int version)
 {
 	amdgpu_bo_handle bo_shader_ps, bo_shader_vs;
 	void *ptr_shader_ps;
@@ -3471,14 +3742,15 @@ static void amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
 	CU_ASSERT_EQUAL(r, 0);
 	memset(ptr_shader_vs, 0, bo_shader_size);
 
-	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST);
+	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST, version);
 	CU_ASSERT_EQUAL(r, 0);
 
-	r = amdgpu_draw_load_vs_shader(ptr_shader_vs);
+	r = amdgpu_draw_load_vs_shader(ptr_shader_vs, version);
 	CU_ASSERT_EQUAL(r, 0);
 
 	amdgpu_memset_draw(device_handle, bo_shader_ps, bo_shader_vs,
-			mc_address_shader_ps, mc_address_shader_vs, ring);
+			mc_address_shader_ps, mc_address_shader_vs,
+			ring, version);
 
 	r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_size);
 	CU_ASSERT_EQUAL(r, 0);
@@ -3492,7 +3764,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
 			       amdgpu_bo_handle bo_shader_vs,
 			       uint64_t mc_address_shader_ps,
 			       uint64_t mc_address_shader_vs,
-			       uint32_t ring, int hang)
+			       uint32_t ring, int version, int hang)
 {
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo_dst, bo_src, bo_cmd, resources[5];
@@ -3536,24 +3808,36 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
 	memset(ptr_src, 0x55, bo_size);
 
 	i = 0;
-	i += amdgpu_draw_init(ptr_cmd + i);
+	i += amdgpu_draw_init(ptr_cmd + i, version);
 
-	i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 0);
+	i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, version, 0);
 
-	i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 0);
+	i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, version, 0);
 
-	i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs, 0);
+	i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs,
+						    version, 0);
 
-	i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps);
+	i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps, version);
 
 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 8);
-	ptr_cmd[i++] = 0xc;
-	ptr_cmd[i++] = mc_address_src >> 8;
-	ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000;
-	ptr_cmd[i++] = 0x7c01f;
-	ptr_cmd[i++] = 0x90500fac;
-	ptr_cmd[i++] = 0x3e000;
-	i += 3;
+	if (version == 9) {
+		ptr_cmd[i++] = 0xc;
+		ptr_cmd[i++] = mc_address_src >> 8;
+		ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000;
+		ptr_cmd[i++] = 0x7c01f;
+		ptr_cmd[i++] = 0x90500fac;
+		ptr_cmd[i++] = 0x3e000;
+		i += 3;
+	} else if (version == 10) {
+		ptr_cmd[i++] = 0xc;
+		ptr_cmd[i++] = mc_address_src >> 8;
+		ptr_cmd[i++] = mc_address_src >> 40 | 0xc4b00000;
+		ptr_cmd[i++] = 0x8007c007;
+		ptr_cmd[i++] = 0x90500fac;
+		i += 2;
+		ptr_cmd[i++] = 0x400;
+		i++;
+	}
 
 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
 	ptr_cmd[i++] = 0x14;
@@ -3564,7 +3848,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
 	ptr_cmd[i++] = 0x191;
 	ptr_cmd[i++] = 0;
 
-	i += amdgpu_draw_draw(ptr_cmd + i);
+	i += amdgpu_draw_draw(ptr_cmd + i, version);
 
 	while (i & 7)
 		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
@@ -3630,7 +3914,7 @@ static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
 }
 
 void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring,
-			     int hang)
+			     int version, int hang)
 {
 	amdgpu_bo_handle bo_shader_ps, bo_shader_vs;
 	void *ptr_shader_ps;
@@ -3655,14 +3939,15 @@ void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring,
 	CU_ASSERT_EQUAL(r, 0);
 	memset(ptr_shader_vs, 0, bo_shader_size);
 
-	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, ps_type);
+	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, ps_type, version);
 	CU_ASSERT_EQUAL(r, 0);
 
-	r = amdgpu_draw_load_vs_shader(ptr_shader_vs);
+	r = amdgpu_draw_load_vs_shader(ptr_shader_vs, version);
 	CU_ASSERT_EQUAL(r, 0);
 
 	amdgpu_memcpy_draw(device_handle, bo_shader_ps, bo_shader_vs,
-			mc_address_shader_ps, mc_address_shader_vs, ring, hang);
+			mc_address_shader_ps, mc_address_shader_vs,
+			ring, version, hang);
 
 	r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_size);
 	CU_ASSERT_EQUAL(r, 0);
@@ -3675,20 +3960,26 @@ static void amdgpu_draw_test(void)
 {
 	int r;
 	struct drm_amdgpu_info_hw_ip info;
-	uint32_t ring_id;
+	uint32_t ring_id, version;
 
 	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
 	CU_ASSERT_EQUAL(r, 0);
 	if (!info.available_rings)
 		printf("SKIP ... as there's no graphics ring\n");
 
+	version = info.hw_ip_version_major;
+	if (version != 9 && version != 10) {
+		printf("SKIP ... unsupported gfx version %d\n", version);
+		return;
+	}
+
 	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
-		amdgpu_memset_draw_test(device_handle, ring_id);
-		amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
+		amdgpu_memset_draw_test(device_handle, ring_id, version);
+		amdgpu_memcpy_draw_test(device_handle, ring_id, version, 0);
 	}
 }
 
-void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring)
+void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring, int version)
 {
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo_shader_ps, bo_shader_vs;
@@ -3744,7 +4035,7 @@ void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint3
 	r = amdgpu_draw_load_ps_shader_hang_slow(ptr_shader_ps, gpu_info.family_id);
 	CU_ASSERT_EQUAL(r, 0);
 
-	r = amdgpu_draw_load_vs_shader(ptr_shader_vs);
+	r = amdgpu_draw_load_vs_shader(ptr_shader_vs, version);
 	CU_ASSERT_EQUAL(r, 0);
 
 	r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096,
@@ -3762,25 +4053,35 @@ void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint3
 	memset(ptr_src, 0x55, bo_size);
 
 	i = 0;
-	i += amdgpu_draw_init(ptr_cmd + i);
+	i += amdgpu_draw_init(ptr_cmd + i, version);
 
-	i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, 1);
+	i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst, version, 1);
 
-	i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, 1);
+	i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i, version, 1);
 
 	i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX,
-							mc_address_shader_vs, 1);
+							mc_address_shader_vs, version, 1);
 
-	i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps);
+	i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps, version);
 
 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 8);
-	ptr_cmd[i++] = 0xc;
-	ptr_cmd[i++] = mc_address_src >> 8;
-	ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000;
-	ptr_cmd[i++] = 0x1ffc7ff;
-	ptr_cmd[i++] = 0x90500fac;
-	ptr_cmd[i++] = 0xffe000;
-	i += 3;
+
+	if (version == 9) {
+		ptr_cmd[i++] = 0xc;
+		ptr_cmd[i++] = mc_address_src >> 8;
+		ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000;
+		ptr_cmd[i++] = 0x1ffcfff;
+		ptr_cmd[i++] = 0x90500fac;
+		ptr_cmd[i++] = 0x1ffe000;
+		i += 3;
+	} else if (version == 10) {
+		ptr_cmd[i++] = 0xc;
+		ptr_cmd[i++] = mc_address_src >> 8;
+		ptr_cmd[i++] = mc_address_src >> 40 | 0xc4b00000;
+		ptr_cmd[i++] = 0x81ffc1ff;
+		ptr_cmd[i++] = 0x90500fac;
+		i += 4;
+	}
 
 	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
 	ptr_cmd[i++] = 0x14;
@@ -3791,7 +4092,7 @@ void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint3
 	ptr_cmd[i++] = 0x191;
 	ptr_cmd[i++] = 0;
 
-	i += amdgpu_draw_draw(ptr_cmd + i);
+	i += amdgpu_draw_draw(ptr_cmd + i, version);
 
 	while (i & 7)
 		ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index 0f780d48..f29a83ab 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -533,32 +533,44 @@ static void amdgpu_draw_hang_gfx(void)
 {
 	int r;
 	struct drm_amdgpu_info_hw_ip info;
-	uint32_t ring_id;
+	uint32_t ring_id, version;
 
 	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
 	CU_ASSERT_EQUAL(r, 0);
 	if (!info.available_rings)
 		printf("SKIP ... as there's no graphic ring\n");
 
+	version = info.hw_ip_version_major;
+	if (version != 9 && version != 10) {
+		printf("SKIP ... unsupported gfx version %d\n", version);
+		return;
+	}
+
 	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
-		amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
-		amdgpu_memcpy_draw_test(device_handle, ring_id, 1);
-		amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
+		amdgpu_memcpy_draw_test(device_handle, ring_id, version, 0);
+		amdgpu_memcpy_draw_test(device_handle, ring_id, version, 1);
+		amdgpu_memcpy_draw_test(device_handle, ring_id, version, 0);
 	}
 }
 
 static void amdgpu_draw_hang_slow_gfx(void)
 {
 	struct drm_amdgpu_info_hw_ip info;
-	uint32_t ring_id;
+	uint32_t ring_id, version;
 	int r;
 
 	r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
 	CU_ASSERT_EQUAL(r, 0);
 
+	version = info.hw_ip_version_major;
+	if (version != 9 && version != 10) {
+		printf("SKIP ... unsupported gfx version %d\n", version);
+		return;
+	}
+
 	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
-		amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
-		amdgpu_memcpy_draw_hang_slow_test(device_handle, ring_id);
-		amdgpu_memcpy_draw_test(device_handle, ring_id, 0);
+		amdgpu_memcpy_draw_test(device_handle, ring_id, version, 0);
+		amdgpu_memcpy_draw_hang_slow_test(device_handle, ring_id, version);
+		amdgpu_memcpy_draw_test(device_handle, ring_id, version, 0);
 	}
 }