diff options
Diffstat (limited to 'libc/sysdeps/sparc')
77 files changed, 3102 insertions, 232 deletions
diff --git a/libc/sysdeps/sparc/fpu/libm-test-ulps b/libc/sysdeps/sparc/fpu/libm-test-ulps index d2770442a..f282a160a 100644 --- a/libc/sysdeps/sparc/fpu/libm-test-ulps +++ b/libc/sysdeps/sparc/fpu/libm-test-ulps @@ -198,6 +198,42 @@ double: 1 idouble: 1 ildouble: 1 ldouble: 1 +Test "Real part of: cacos (-0.5 + +0 i) == 2.094395102393195492308428922186335256131 - 0 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: cacos (-0.5 - 0 i) == 2.094395102393195492308428922186335256131 + +0 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (-0x1p500 + 1.0 i) == 3.141592653589793238462643383279502884197 - 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (-0x1p500 - 1.0 i) == 3.141592653589793238462643383279502884197 + 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (-0x1p5000 + 1.0 i) == 3.141592653589793238462643383279502884197 - 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (-0x1p5000 - 1.0 i) == 3.141592653589793238462643383279502884197 + 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: cacos (-1.0 + 0x1p50 i) == 1.570796326794897507409741391764983781004 - 3.535050620855721078027883819436759661753e1 i": +float: 1 +ifloat: 1 +Test "Imaginary part of: cacos (-1.0 + 0x1p500 i) == 1.570796326794896619231321691639751442099 - 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (-1.0 + 0x1p5000 i) == 1.570796326794896619231321691639751442099 - 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: cacos (-1.0 - 0x1p50 i) == 1.570796326794897507409741391764983781004 + 3.535050620855721078027883819436759661753e1 i": +float: 1 +ifloat: 1 +Test "Imaginary part of: cacos (-1.0 - 0x1p500 i) == 1.570796326794896619231321691639751442099 + 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (-1.0 - 0x1p5000 i) == 1.570796326794896619231321691639751442099 + 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 Test "Imaginary part of: cacos (-1.5 + +0 i) == pi - 0.9624236501192068949955178268487368462704 i": double: 1 float: 1 @@ -205,6 +241,11 @@ idouble: 1 ifloat: 1 ildouble: 1 ldouble: 1 +Test "Real part of: cacos (-2 - 3 i) == 2.1414491111159960199416055713254211 + 1.9833870299165354323470769028940395 i": +float: 1 +ifloat: 1 +ildouble: 1 +ldouble: 1 Test "Real part of: cacos (0.5 + +0 i) == 1.047197551196597746154214461093167628066 - 0 i": double: 1 idouble: 1 @@ -221,6 +262,39 @@ ifloat: 1 Test "Imaginary part of: cacos (0.75 + 1.25 i) == 1.11752014915610270578240049553777969 - 1.13239363160530819522266333696834467 i": ildouble: 1 ldouble: 1 +Test "Imaginary part of: cacos (0x1.fp1023 + 0x1.fp1023 i) == 7.853981633974483096156608458198757210493e-1 - 7.107906849659093345062145442726115449315e2 i": +double: 1 +idouble: 1 +Test "Imaginary part of: cacos (0x1.fp127 + 0x1.fp127 i) == 7.853981633974483096156608458198757210493e-1 - 8.973081118419833726837456344608533993585e1 i": +double: 1 +idouble: 1 +Test "Imaginary part of: cacos (0x1.fp16383 + 0x1.fp16383 i) == 7.853981633974483096156608458198757210493e-1 - 1.135753137836666928715489992987020363057e4 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (0x1p500 + 1.0 i) == 3.054936363499604682051979393213617699789e-151 - 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (0x1p500 - 1.0 i) == 3.054936363499604682051979393213617699789e-151 + 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (0x1p5000 + 1.0 i) == 7.079811261048172892385615158694057552948e-1506 - 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (0x1p5000 - 1.0 i) == 7.079811261048172892385615158694057552948e-1506 + 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (1.0 + 0x1p500 i) == 1.570796326794896619231321691639751442099 - 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (1.0 + 0x1p5000 i) == 1.570796326794896619231321691639751442099 - 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (1.0 - 0x1p500 i) == 1.570796326794896619231321691639751442099 + 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: cacos (1.0 - 0x1p5000 i) == 1.570796326794896619231321691639751442099 + 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 Test "Imaginary part of: cacos (1.5 + +0 i) == +0 - 0.9624236501192068949955178268487368462704 i": double: 1 float: 1 @@ -407,6 +481,30 @@ double: 1 idouble: 1 ildouble: 1 ldouble: 1 +Test "Imaginary part of: casin (-0x1p500 + 1.0 i) == -1.570796326794896619231321691639751442099 + 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (-0x1p500 - 1.0 i) == -1.570796326794896619231321691639751442099 - 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (-0x1p5000 + 1.0 i) == -1.570796326794896619231321691639751442099 + 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (-0x1p5000 - 1.0 i) == -1.570796326794896619231321691639751442099 - 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (-1.0 + 0x1p500 i) == -3.054936363499604682051979393213617699789e-151 + 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (-1.0 + 0x1p5000 i) == -7.079811261048172892385615158694057552948e-1506 + 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (-1.0 - 0x1p500 i) == -3.054936363499604682051979393213617699789e-151 - 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (-1.0 - 0x1p5000 i) == -7.079811261048172892385615158694057552948e-1506 - 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 Test "Imaginary part of: casin (-1.5 + +0 i) == -pi/2 + 0.9624236501192068949955178268487368462704 i": double: 1 float: 1 @@ -422,6 +520,39 @@ ifloat: 1 Test "Imaginary part of: casin (0.75 + 1.25 i) == 0.453276177638793913448921196101971749 + 1.13239363160530819522266333696834467 i": ildouble: 1 ldouble: 1 +Test "Imaginary part of: casin (0x1.fp1023 + 0x1.fp1023 i) == 7.853981633974483096156608458198757210493e-1 + 7.107906849659093345062145442726115449315e2 i": +double: 1 +idouble: 1 +Test "Imaginary part of: casin (0x1.fp127 + 0x1.fp127 i) == 7.853981633974483096156608458198757210493e-1 + 8.973081118419833726837456344608533993585e1 i": +double: 1 +idouble: 1 +Test "Imaginary part of: casin (0x1.fp16383 + 0x1.fp16383 i) == 7.853981633974483096156608458198757210493e-1 + 1.135753137836666928715489992987020363057e4 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (0x1p500 + 1.0 i) == 1.570796326794896619231321691639751442099 + 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (0x1p500 - 1.0 i) == 1.570796326794896619231321691639751442099 - 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (0x1p5000 + 1.0 i) == 1.570796326794896619231321691639751442099 + 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (0x1p5000 - 1.0 i) == 1.570796326794896619231321691639751442099 - 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (1.0 + 0x1p500 i) == 3.054936363499604682051979393213617699789e-151 + 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (1.0 + 0x1p5000 i) == 7.079811261048172892385615158694057552948e-1506 + 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (1.0 - 0x1p500 i) == 3.054936363499604682051979393213617699789e-151 - 3.472667374605326000180332928505464606058e2 i": +ildouble: 1 +ldouble: 1 +Test "Imaginary part of: casin (1.0 - 0x1p5000 i) == 7.079811261048172892385615158694057552948e-1506 - 3.466429049980286492395577839412341016946e3 i": +ildouble: 1 +ldouble: 1 Test "Imaginary part of: casin (1.5 + +0 i) == pi/2 + 0.9624236501192068949955178268487368462704 i": double: 1 float: 1 @@ -459,6 +590,18 @@ idouble: 2 ifloat: 1 ildouble: 1 ldouble: 1 +Test "Real part of: casinh (-0x1p500 + 1.0 i) == -3.472667374605326000180332928505464606058e2 + 3.054936363499604682051979393213617699789e-151 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (-0x1p500 - 1.0 i) == -3.472667374605326000180332928505464606058e2 - 3.054936363499604682051979393213617699789e-151 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (-0x1p5000 + 1.0 i) == -3.466429049980286492395577839412341016946e3 + 7.079811261048172892385615158694057552948e-1506 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (-0x1p5000 - 1.0 i) == -3.466429049980286492395577839412341016946e3 - 7.079811261048172892385615158694057552948e-1506 i": +ildouble: 1 +ldouble: 1 Test "Real part of: casinh (-1.0 + +0 i) == -0.8813735870195430252326093249797923090282 + +0 i": double: 2 float: 1 @@ -466,6 +609,12 @@ idouble: 2 ifloat: 1 ildouble: 3 ldouble: 3 +Test "Real part of: casinh (-1.0 + 0x1p500 i) == -3.472667374605326000180332928505464606058e2 + 1.570796326794896619231321691639751442099 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (-1.0 + 0x1p5000 i) == -3.466429049980286492395577839412341016946e3 + 1.570796326794896619231321691639751442099 i": +ildouble: 1 +ldouble: 1 Test "Real part of: casinh (-1.0 - 0 i) == -0.8813735870195430252326093249797923090282 - 0 i": double: 2 float: 1 @@ -473,6 +622,12 @@ idouble: 2 ifloat: 1 ildouble: 3 ldouble: 3 +Test "Real part of: casinh (-1.0 - 0x1p500 i) == -3.472667374605326000180332928505464606058e2 - 1.570796326794896619231321691639751442099 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (-1.0 - 0x1p5000 i) == -3.466429049980286492395577839412341016946e3 - 1.570796326794896619231321691639751442099 i": +ildouble: 1 +ldouble: 1 Test "Real part of: casinh (-1.5 + +0 i) == -1.194763217287109304111930828519090523536 + +0 i": double: 2 float: 1 @@ -523,6 +678,27 @@ idouble: 1 ifloat: 1 ildouble: 1 ldouble: 1 +Test "Real part of: casinh (0x1.fp1023 + 0x1.fp1023 i) == 7.107906849659093345062145442726115449315e2 + 7.853981633974483096156608458198757210493e-1 i": +double: 1 +idouble: 1 +Test "Real part of: casinh (0x1.fp127 + 0x1.fp127 i) == 8.973081118419833726837456344608533993585e1 + 7.853981633974483096156608458198757210493e-1 i": +double: 1 +idouble: 1 +Test "Real part of: casinh (0x1.fp16383 + 0x1.fp16383 i) == 1.135753137836666928715489992987020363057e4 + 7.853981633974483096156608458198757210493e-1 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (0x1p500 + 1.0 i) == 3.472667374605326000180332928505464606058e2 + 3.054936363499604682051979393213617699789e-151 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (0x1p500 - 1.0 i) == 3.472667374605326000180332928505464606058e2 - 3.054936363499604682051979393213617699789e-151 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (0x1p5000 + 1.0 i) == 3.466429049980286492395577839412341016946e3 + 7.079811261048172892385615158694057552948e-1506 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (0x1p5000 - 1.0 i) == 3.466429049980286492395577839412341016946e3 - 7.079811261048172892385615158694057552948e-1506 i": +ildouble: 1 +ldouble: 1 Test "Real part of: casinh (1.0 + +0 i) == 0.8813735870195430252326093249797923090282 + +0 i": double: 1 float: 1 @@ -530,6 +706,12 @@ idouble: 1 ifloat: 1 ildouble: 1 ldouble: 1 +Test "Real part of: casinh (1.0 + 0x1p500 i) == 3.472667374605326000180332928505464606058e2 + 1.570796326794896619231321691639751442099 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (1.0 + 0x1p5000 i) == 3.466429049980286492395577839412341016946e3 + 1.570796326794896619231321691639751442099 i": +ildouble: 1 +ldouble: 1 Test "Real part of: casinh (1.0 - 0 i) == 0.8813735870195430252326093249797923090282 - 0 i": double: 1 float: 1 @@ -537,6 +719,12 @@ idouble: 1 ifloat: 1 ildouble: 1 ldouble: 1 +Test "Real part of: casinh (1.0 - 0x1p500 i) == 3.472667374605326000180332928505464606058e2 - 1.570796326794896619231321691639751442099 i": +ildouble: 1 +ldouble: 1 +Test "Real part of: casinh (1.0 - 0x1p5000 i) == 3.466429049980286492395577839412341016946e3 - 1.570796326794896619231321691639751442099 i": +ildouble: 1 +ldouble: 1 Test "Real part of: casinh (1.5 + +0 i) == 1.194763217287109304111930828519090523536 + +0 i": double: 1 idouble: 1 diff --git a/libc/sysdeps/sparc/sparc-ifunc.h b/libc/sysdeps/sparc/sparc-ifunc.h index edff5c880..f68161fc5 100644 --- a/libc/sysdeps/sparc/sparc-ifunc.h +++ b/libc/sysdeps/sparc/sparc-ifunc.h @@ -51,6 +51,33 @@ ENTRY (__##name) \ mov %o1, %o0; \ END (__##name) +# define SPARC_ASM_IFUNC2(name, m1, f1, m2, f2, dflt) \ +ENTRY (__##name) \ + .type __##name, @gnu_indirect_function; \ + SETUP_PIC_REG_LEAF(o3, o5); \ + set m1, %o1; \ + andcc %o0, %o1, %g0; \ + be 8f; \ + nop; \ + sethi %gdop_hix22(f1), %o1; \ + xor %o1, %gdop_lox10(f1), %o1; \ + ba 10f; \ + nop; \ +8: set m2, %o1; \ + andcc %o0, %o1, %g0; \ + be 9f; \ + nop; \ + sethi %gdop_hix22(f2), %o1; \ + xor %o1, %gdop_lox10(f2), %o1; \ + ba 10f; \ + nop; \ +9: sethi %gdop_hix22(dflt), %o1; \ + xor %o1, %gdop_lox10(dflt), %o1; \ +10: add %o3, %o1, %o1; \ + retl; \ + mov %o1, %o0; \ +END (__##name) + # else /* SHARED */ # ifdef __arch64__ @@ -82,19 +109,54 @@ ENTRY (__##name) \ mov %o1, %o0; \ END (__##name) +# define SPARC_ASM_IFUNC2(name, m1, f1, m2, f2, dflt) \ +ENTRY (__##name) \ + .type __##name, @gnu_indirect_function; \ + set m1, %o1; \ + andcc %o0, %o1, %g0; \ + be 8f; \ + nop; \ + SET(f1, %g1, %o1); \ + ba 10f; \ + nop; \ +8: set m2, %o1; \ + andcc %o0, %o1, %g0; \ + be 9f; \ + nop; \ + SET(f2, %g1, %o1); \ + ba 10f; \ + nop; \ +9: SET(dflt, %g1, %o1); \ +10: retl; \ + mov %o1, %o0; \ +END (__##name) + # endif /* SHARED */ +#define SPARC_ASM_VIS2_IFUNC(name) \ + SPARC_ASM_IFUNC1(name, HWCAP_SPARC_VIS2, \ + __##name##_vis2, __##name##_generic) + # ifdef HAVE_AS_VIS3_SUPPORT #define SPARC_ASM_VIS3_IFUNC(name) \ SPARC_ASM_IFUNC1(name, HWCAP_SPARC_VIS3, \ __##name##_vis3, __##name##_generic) +#define SPARC_ASM_VIS3_VIS2_IFUNC(name) \ + SPARC_ASM_IFUNC2(name, HWCAP_SPARC_VIS3, \ + __##name##_vis3, \ + HWCAP_SPARC_VIS2, \ + __##name##_vis2, __##name##_generic) + # else /* HAVE_AS_VIS3_SUPPORT */ #define SPARC_ASM_VIS3_IFUNC(name) \ SPARC_ASM_IFUNC_DFLT(name, __##name##_generic) +#define SPARC_ASM_VIS3_VIS2_IFUNC(name) \ + SPARC_ASM_VIS2_IFUNC(name) + # endif /* HAVE_AS_VIS3_SUPPORT */ diff --git a/libc/sysdeps/sparc/sparc32/fpu/s_fdim.S b/libc/sysdeps/sparc/sparc32/fpu/s_fdim.S new file mode 100644 index 000000000..2f0c5ce58 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/fpu/s_fdim.S @@ -0,0 +1,41 @@ +/* Compute positive difference, sparc 32-bit. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + +ENTRY(__fdim) + std %o0, [%sp + 72] + std %o2, [%sp + 80] + ldd [%sp + 72], %f0 + ldd [%sp + 80], %f2 + fcmpd %f0, %f2 + st %g0, [%sp + 72] + fbug 1f + st %g0, [%sp + 76] + ldd [%sp + 72], %f0 + fnegd %f0, %f2 +1: retl + fsubd %f0, %f2, %f0 +END(__fdim) +weak_alias (__fdim, fdim) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __fdim, fdiml, GLIBC_2_1); +#endif diff --git a/libc/sysdeps/sparc/sparc32/fpu/s_fdimf.S b/libc/sysdeps/sparc/sparc32/fpu/s_fdimf.S new file mode 100644 index 000000000..570fdc30b --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/fpu/s_fdimf.S @@ -0,0 +1,35 @@ +/* Compute positive difference, sparc 32-bit. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__fdimf) + st %o0, [%sp + 72] + st %o1, [%sp + 76] + ld [%sp + 72], %f0 + ld [%sp + 76], %f1 + fcmps %f0, %f1 + fbug 1f + st %g0, [%sp + 72] + ld [%sp + 72], %f0 + fnegs %f0, %f1 +1: retl + fsubs %f0, %f1, %f0 +END(__fdimf) +weak_alias (__fdimf, fdimf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/addmul_1.S b/libc/sysdeps/sparc/sparc32/sparcv9/addmul_1.S index 563bfb1c0..7ba81d8a6 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/addmul_1.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/addmul_1.S @@ -1 +1,81 @@ -#include <sparcv8/addmul_1.S> +! SPARC v9 32-bit __mpn_addmul_1 -- Multiply a limb vector with a limb +! and add the result to a second limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz_arg %i2 +#define s2l_arg %i3 +#define sz %o4 +#define carry %o5 +#define s2_limb %g1 +#define tmp1 %l0 +#define tmp2 %l1 +#define tmp3 %l2 +#define tmp4 %l3 +#define tmp64_1 %g3 +#define tmp64_2 %o3 + +ENTRY(__mpn_addmul_1) + save %sp, -96, %sp + srl sz_arg, 0, sz + srl s2l_arg, 0, s2_limb + subcc sz, 1, sz + be,pn %icc, .Lfinal_limb + clr carry + +.Lloop: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + lduw [s1_ptr + 0x04], tmp2 + lduw [res_ptr + 0x04], tmp4 + mulx tmp1, s2_limb, tmp64_1 + add s1_ptr, 8, s1_ptr + mulx tmp2, s2_limb, tmp64_2 + sub sz, 2, sz + add res_ptr, 8, res_ptr + add tmp3, tmp64_1, tmp64_1 + add carry, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr - 0x08] + srlx tmp64_1, 32, carry + add tmp4, tmp64_2, tmp64_2 + add carry, tmp64_2, tmp64_2 + stw tmp64_2, [res_ptr - 0x04] + brgz sz, .Lloop + srlx tmp64_2, 32, carry + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp64_1 + add tmp3, tmp64_1, tmp64_1 + add carry, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr + 0x00] + srlx tmp64_1, 32, carry + +.Lfinish: + jmpl %i7 + 0x8, %g0 + restore carry, 0, %o0 +END(__mpn_addmul_1) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile index ee9f6ffce..0d92813d7 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile @@ -1,11 +1,15 @@ ifeq ($(subdir),math) +libm-sysdep_routines += s_ceil-vis2 s_ceilf-vis2 \ + s_floor-vis2 s_floorf-vis2 ifeq ($(have-as-vis3),yes) libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 s_ceilf-vis3 \ s_ceil-vis3 s_fabs-vis3 s_fabsf-vis3 s_floor-vis3 \ s_floorf-vis3 s_llrintf-vis3 s_llrint-vis3 \ s_rintf-vis3 s_rint-vis3 w_sqrt-vis3 w_sqrtf-vis3 \ s_fminf-vis3 s_fmin-vis3 s_fmaxf-vis3 s_fmax-vis3 \ - s_fmaf-vis3 s_fma-vis3 + s_fmaf-vis3 s_fma-vis3 s_fdimf-vis3 s_fdim-vis3 \ + s_nearbyint-vis3 s_nearbyintf-vis3 s_truncf-vis3 \ + s_trunc-vis3 sysdep_routines += s_copysignf-vis3 s_copysign-vis3 endif endif diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis2.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis2.S new file mode 100644 index 000000000..94388003d --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis2.S @@ -0,0 +1,61 @@ +/* ceil function, sparc32 v9 vis2 version. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceil_vis2) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fzero ZERO + ldd [%sp + 72], %f0 + fnegd ZERO, SIGN_BIT + stx %o2, [%sp + 72] + fabsd %f0, %f14 + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 + faddd %f0, %f16, %f18 + siam (1 << 2) | 0 + fsubd %f18, %f16, %f18 + siam (0 << 2) + retl + for %f18, SIGN_BIT, %f0 +END (__ceil_vis2) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S index 0c2140d95..aebff5cae 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S @@ -19,27 +19,21 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_FIFTYTWO 0x43300000 /* 2**52 */ -#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ @@ -47,32 +41,22 @@ ENTRY (__ceil_vis3) sethi %hi(TWO_FIFTYTWO), %o2 sllx %o0, 32, %o0 - sethi %hi(ONE_DOT_ZERO), %o3 + sllx %o2, 32, %o2 or %o0, %o1, %o0 movxtod %o0, %f0 - sllx %o2, 32, %o2 fzero ZERO - sllx %o3, 32, %o3 - fnegd ZERO, SIGN_BIT - movxtod %o2, %f16 fabsd %f0, %f14 - fcmpd %fcc3, %f14, %f16 - fmovduge %fcc3, ZERO, %f16 fand %f0, SIGN_BIT, SIGN_BIT - for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 faddd %f0, %f16, %f18 + siam (1 << 2) | 0 fsubd %f18, %f16, %f18 - fcmpd %fcc2, %f18, %f0 - movxtod %o3, %f20 - - fmovduge %fcc2, ZERO, %f20 - faddd %f18, %f20, %f0 - fabsd %f0, %f0 + siam (0 << 2) retl - for %f0, SIGN_BIT, %f0 + for %f18, SIGN_BIT, %f0 END (__ceil_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S index 835703fb9..efc8d4936 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S @@ -1,7 +1,7 @@ #include <sparc-ifunc.h> #include <math_ldbl_opt.h> -SPARC_ASM_VIS3_IFUNC(ceil) +SPARC_ASM_VIS3_VIS2_IFUNC(ceil) weak_alias (__ceil, ceil) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis2.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis2.S new file mode 100644 index 000000000..bc516765f --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis2.S @@ -0,0 +1,58 @@ +/* Float ceil function, sparc32 v9 vis2 version. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceilf_vis2) + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + ld [%sp + 68], %f0 + fnegs ZERO, SIGN_BIT + st %o2, [%sp + 68] + fabss %f0, %f14 + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 + fadds %f0, %f16, %f1 + siam (1 << 2) | 0 + fsubs %f1, %f16, %f1 + siam (0 << 2) + retl + fors %f1, SIGN_BIT, %f0 +END (__ceilf_vis2) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S index 7d30c0b84..0a6768ca1 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S @@ -19,27 +19,21 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ -#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ @@ -47,28 +41,19 @@ ENTRY (__ceilf_vis3) movwtos %o0, %f0 sethi %hi(TWO_TWENTYTHREE), %o2 - sethi %hi(ONE_DOT_ZERO), %o3 fzeros ZERO - fnegs ZERO, SIGN_BIT - movwtos %o2, %f16 fabss %f0, %f14 - fcmps %fcc3, %f14, %f16 - fmovsuge %fcc3, ZERO, %f16 fands %f0, SIGN_BIT, SIGN_BIT - fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 fadds %f0, %f16, %f1 + siam (1 << 2) | 0 fsubs %f1, %f16, %f1 - fcmps %fcc2, %f1, %f0 - movwtos %o3, %f9 - - fmovsuge %fcc2, ZERO, %f9 - fadds %f1, %f9, %f0 - fabss %f0, %f0 + siam (0 << 2) retl - fors %f0, SIGN_BIT, %f0 + fors %f1, SIGN_BIT, %f0 END (__ceilf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S index 3047dd8fa..1c72a5728 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S @@ -1,6 +1,6 @@ #include <sparc-ifunc.h> -SPARC_ASM_VIS3_IFUNC(ceilf) +SPARC_ASM_VIS3_VIS2_IFUNC(ceilf) weak_alias (__ceilf, ceilf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.S new file mode 100644 index 000000000..5e011a121 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.S @@ -0,0 +1,34 @@ +/* Compute positive difference, sparc 32-bit+v9+vis3. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__fdim_vis3) + movwtos %o0, %f0 + movwtos %o1, %f1 + movwtos %o2, %f2 + movwtos %o3, %f3 + fcmpd %f0, %f2 + fbug 1f + nop + fzero %f0 + fnegd %f0, %f2 +1: retl + fsubd %f0, %f2, %f0 +END(__fdim_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.S new file mode 100644 index 000000000..4b1340824 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.S @@ -0,0 +1,19 @@ +#include <sparc-ifunc.h> +#include <math_ldbl_opt.h> + +SPARC_ASM_VIS3_IFUNC(fdim) + +weak_alias (__fdim, fdim) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __fdim, fdiml, GLIBC_2_1); +#endif + +# undef weak_alias +# define weak_alias(a, b) +# undef compat_symbol +# define compat_symbol(a, b, c, d) + +#define __fdim __fdim_generic + +#include "../s_fdim.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.S new file mode 100644 index 000000000..c6d571297 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.S @@ -0,0 +1,32 @@ +/* Compute positive difference, sparc 32-bit+v9+vis3. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__fdimf_vis3) + movwtos %o0, %f0 + movwtos %o1, %f1 + fcmps %f0, %f1 + fbug 1f + nop + fzeros %f0 + fnegs %f0, %f1 +1: retl + fsubs %f0, %f1, %f0 +END(__fdimf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.S new file mode 100644 index 000000000..30381d6a5 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(fdimf) + +weak_alias (__fdimf, fdimf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fdimf __fdimf_generic + +#include "../s_fdimf.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis2.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis2.S new file mode 100644 index 000000000..3b5e8fd7c --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis2.S @@ -0,0 +1,61 @@ +/* floor function, sparc32 v9 vis2 version. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floor_vis2) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fzero ZERO + ldd [%sp + 72], %f0 + fnegd ZERO, SIGN_BIT + stx %o2, [%sp + 72] + fabsd %f0, %f14 + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 + faddd %f0, %f16, %f18 + siam (1 << 2) | 0 + fsubd %f18, %f16, %f18 + siam (0 << 2) + retl + for %f18, SIGN_BIT, %f0 +END (__floor_vis2) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S index 8445f1d7a..41fdfac3b 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S @@ -19,27 +19,21 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_FIFTYTWO 0x43300000 /* 2**52 */ -#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ @@ -47,32 +41,22 @@ ENTRY (__floor_vis3) sethi %hi(TWO_FIFTYTWO), %o2 sllx %o0, 32, %o0 - sethi %hi(ONE_DOT_ZERO), %o3 + sllx %o2, 32, %o2 or %o0, %o1, %o0 movxtod %o0, %f0 - sllx %o2, 32, %o2 fzero ZERO - sllx %o3, 32, %o3 - fnegd ZERO, SIGN_BIT - movxtod %o2, %f16 fabsd %f0, %f14 - fcmpd %fcc3, %f14, %f16 - fmovduge %fcc3, ZERO, %f16 fand %f0, SIGN_BIT, SIGN_BIT - for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 faddd %f0, %f16, %f18 + siam (1 << 2) | 0 fsubd %f18, %f16, %f18 - fcmpd %fcc2, %f18, %f0 - movxtod %o3, %f20 - - fmovdule %fcc2, ZERO, %f20 - fsubd %f18, %f20, %f0 - fabsd %f0, %f0 + siam (0 << 2) retl - for %f0, SIGN_BIT, %f0 + for %f18, SIGN_BIT, %f0 END (__floor_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S index 37aeb43b9..1fe4b95ea 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S @@ -1,7 +1,7 @@ #include <sparc-ifunc.h> #include <math_ldbl_opt.h> -SPARC_ASM_VIS3_IFUNC(floor) +SPARC_ASM_VIS3_VIS2_IFUNC(floor) weak_alias (__floor, floor) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis2.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis2.S new file mode 100644 index 000000000..4f731212e --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis2.S @@ -0,0 +1,58 @@ +/* Float floor function, sparc32 v9 vis2 version. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floorf_vis2) + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + ld [%sp + 68], %f0 + fnegs ZERO, SIGN_BIT + st %o2, [%sp + 68] + fabss %f0, %f14 + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 + fadds %f0, %f16, %f1 + siam (1 << 2) | 0 + fsubs %f1, %f16, %f1 + siam (0 << 2) + retl + fors %f1, SIGN_BIT, %f0 +END (__floorf_vis2) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S index 133a0a4a9..fe2d2da20 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S @@ -19,27 +19,21 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ -#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ @@ -47,28 +41,19 @@ ENTRY (__floorf_vis3) movwtos %o0, %f0 sethi %hi(TWO_TWENTYTHREE), %o2 - sethi %hi(ONE_DOT_ZERO), %o3 fzeros ZERO - fnegs ZERO, SIGN_BIT - movwtos %o2, %f16 fabss %f0, %f14 - fcmps %fcc3, %f14, %f16 - fmovsuge %fcc3, ZERO, %f16 fands %f0, SIGN_BIT, SIGN_BIT - fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 fadds %f0, %f16, %f1 + siam (1 << 2) | 0 fsubs %f1, %f16, %f1 - fcmps %fcc2, %f1, %f0 - movwtos %o3, %f9 - - fmovsule %fcc2, ZERO, %f9 - fsubs %f1, %f9, %f0 - fabss %f0, %f0 + siam (0 << 2) retl - fors %f0, SIGN_BIT, %f0 + fors %f1, SIGN_BIT, %f0 END (__floorf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S index 31cda385b..d2a83cb9b 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S @@ -1,6 +1,6 @@ #include <sparc-ifunc.h> -SPARC_ASM_VIS3_IFUNC(floorf) +SPARC_ASM_VIS3_VIS2_IFUNC(floorf) weak_alias (__floorf, floorf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S new file mode 100644 index 000000000..b509500ed --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S @@ -0,0 +1,65 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint_vis3) + st %fsr, [%sp + 88] + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + sllx %o0, 32, %o0 + or %o5, %lo(0xf8003e0), %o5 + or %o0, %o1, %o0 + movxtod %o0, %f0 + andn %o4, %o5, %o4 + fzero ZERO + st %o4, [%sp + 80] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + ld [%sp + 80], %fsr + movxtod %o2, %f16 + fabsd %f0, %f14 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyint_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint.S new file mode 100644 index 000000000..47da9eaaf --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint.S @@ -0,0 +1,19 @@ +#include <sparc-ifunc.h> +#include <math_ldbl_opt.h> + +SPARC_ASM_VIS3_IFUNC(nearbyint) + +weak_alias (__nearbyint, nearbyint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __nearbyint, nearbyintl, GLIBC_2_1) +#endif + +# undef weak_alias +# define weak_alias(a, b) +# undef compat_symbol +# define compat_symbol(a, b, c, d) + +#define __nearbyint __nearbyint_generic + +#include "../s_nearbyint.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S new file mode 100644 index 000000000..336126dee --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S @@ -0,0 +1,61 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf_vis3) + st %fsr, [%sp + 88] + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + fzeros ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegs ZERO, SIGN_BIT + andn %o4, %o5, %o4 + st %o4, [%sp + 80] + ld [%sp + 80], %fsr + movwtos %o2, %f16 + fabss %f1, %f14 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyintf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S new file mode 100644 index 000000000..95100c1bf --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(nearbyintf) + +weak_alias (__nearbyintf, nearbyintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __nearbyintf __nearbyintf_generic + +#include "../s_nearbyintf.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc-vis3.S new file mode 100644 index 000000000..72ec2826e --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc-vis3.S @@ -0,0 +1,57 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc32 v9 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__trunc_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + fzero ZERO + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + movxtod %o2, %f16 + fabsd %f0, %f14 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f14 + fand %f0, SIGN_BIT, SIGN_BIT + fdtox %f14, %f14 + fxtod %f14, %f14 + faddd %f0, ZERO, %f18 + fmovduge %fcc3, %f18, %f14 + retl + for %f14, SIGN_BIT, %f0 +END (__trunc_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc.S new file mode 100644 index 000000000..3787fa1f1 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc.S @@ -0,0 +1,19 @@ +#include <sparc-ifunc.h> +#include <math_ldbl_opt.h> + +SPARC_ASM_VIS3_IFUNC(trunc) + +weak_alias (__trunc, trunc) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __trunc, truncl, GLIBC_2_1) +#endif + +# undef weak_alias +# define weak_alias(a, b) +# undef compat_symbol +# define compat_symbol(a, b, c, d) + +#define __trunc __trunc_generic + +#include "../s_trunc.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf-vis3.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf-vis3.S new file mode 100644 index 000000000..60445dfaa --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf-vis3.S @@ -0,0 +1,53 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc32 v9 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__truncf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + fabss %f1, %f14 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f14 + fands %f1, SIGN_BIT, SIGN_BIT + fstoi %f14, %f14 + fitos %f14, %f14 + fadds %f1, ZERO, %f18 + fmovsuge %fcc3, %f18, %f14 + retl + fors %f14, SIGN_BIT, %f0 +END (__truncf_vis3) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf.S new file mode 100644 index 000000000..2ca251733 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(truncf) + +weak_alias (__truncf, truncf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __truncf __truncf_generic + +#include "../s_truncf.S" diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdim.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdim.S new file mode 100644 index 000000000..6f26ab7af --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdim.S @@ -0,0 +1,40 @@ +/* Compute positive difference, sparc 32-bit+v9. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + +ENTRY(__fdim) + std %o0, [%sp + 72] + std %o2, [%sp + 80] + ldd [%sp + 72], %f0 + ldd [%sp + 80], %f2 + fcmpd %f0, %f2 + fbug 1f + nop + fzero %f0 + fnegd %f0, %f2 +1: retl + fsubd %f0, %f2, %f0 +END(__fdim) +weak_alias (__fdim, fdim) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __fdim, fdiml, GLIBC_2_1); +#endif diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdimf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdimf.S new file mode 100644 index 000000000..fc55867cd --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_fdimf.S @@ -0,0 +1,35 @@ +/* Compute positive difference, sparc 32-bit+v9. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__fdimf) + st %o0, [%sp + 72] + st %o1, [%sp + 76] + ld [%sp + 72], %f0 + ld [%sp + 76], %f1 + fcmps %f0, %f1 + fbug 1f + nop + fzeros %f0 + fnegs %f0, %f1 +1: retl + fsubs %f0, %f1, %f0 +END(__fdimf) +weak_alias (__fdimf, fdimf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S new file mode 100644 index 000000000..ee6a575e1 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S @@ -0,0 +1,72 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint) + st %fsr, [%sp + 88] + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + sllx %o0, 32, %o0 + or %o5, %lo(0xf8003e0), %o5 + or %o0, %o1, %o0 + andn %o4, %o5, %o4 + fzero ZERO + st %o4, [%sp + 80] + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + ldd [%sp + 72], %f0 + ld [%sp + 80], %fsr + stx %o2, [%sp + 72] + fabsd %f0, %f14 + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyint) +weak_alias (__nearbyint, nearbyint) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __nearbyint, nearbyintl, GLIBC_2_1) +#endif diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S new file mode 100644 index 000000000..4225b5449 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S @@ -0,0 +1,64 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc32 v9 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf) + st %fsr, [%sp + 88] + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(0xf8003e0), %o5 + ld [%sp + 88], %o4 + fzeros ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegs ZERO, SIGN_BIT + andn %o4, %o5, %o4 + st %o4, [%sp + 80] + ld [%sp + 68], %f1 + ld [%sp + 80], %fsr + st %o2, [%sp + 68] + fabss %f1, %f14 + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ld [%sp + 88], %fsr +END (__nearbyintf) +weak_alias (__nearbyintf, nearbyintf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_trunc.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_trunc.S new file mode 100644 index 000000000..c451d1d99 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_trunc.S @@ -0,0 +1,64 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc32 v9 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__trunc) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + or %o0, %o1, %o0 + fzero ZERO + stx %o0, [%sp + 72] + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + ldd [%sp + 72], %f0 + stx %o2, [%sp + 72] + fabsd %f0, %f14 + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f14 + fand %f0, SIGN_BIT, SIGN_BIT + fdtox %f14, %f14 + fxtod %f14, %f14 + faddd %f0, ZERO, %f18 + fmovduge %fcc3, %f18, %f14 + retl + for %f14, SIGN_BIT, %f0 +END (__trunc) +weak_alias (__trunc, trunc) + +#if LONG_DOUBLE_COMPAT(libm, GLIBC_2_1) +compat_symbol (libm, __trunc, truncl, GLIBC_2_1) +#endif diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_truncf.S b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_truncf.S new file mode 100644 index 000000000..4e6e25b26 --- /dev/null +++ b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/s_truncf.S @@ -0,0 +1,56 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc32 v9 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__truncf) + st %o0, [%sp + 68] + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + ld [%sp + 68], %f1 + fnegs ZERO, SIGN_BIT + st %o2, [%sp + 68] + fabss %f1, %f14 + ld [%sp + 68], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f14 + fands %f1, SIGN_BIT, SIGN_BIT + fstoi %f14, %f14 + fitos %f14, %f14 + fadds %f1, ZERO, %f18 + fmovsuge %fcc3, %f18, %f14 + retl + fors %f14, SIGN_BIT, %f0 +END (__truncf) +weak_alias (__truncf, truncf) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies b/libc/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies deleted file mode 100644 index a380d8a73..000000000 --- a/libc/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies +++ /dev/null @@ -1,4 +0,0 @@ -# We must list this here to move it ahead of the ldbl-opt code. -sparc/sparc32/sparcv9/fpu/multiarch -sparc/sparc32/sparcv9/fpu -sparc/sparc32/fpu diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/mul_1.S b/libc/sysdeps/sparc/sparc32/sparcv9/mul_1.S index 42284eada..e9a537196 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/mul_1.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/mul_1.S @@ -1 +1,70 @@ -#include <sparcv8/mul_1.S> +! SPARC v9 32-bit __mpn_mul_1 -- Multiply a limb vector with a single +! limb and store the product in a second limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %o0 +#define s1_ptr %o1 +#define sz %o2 +#define s2_limb %o3 +#define carry %o5 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 + +ENTRY(__mpn_mul_1) + srl sz, 0, sz + srl s2_limb, 0, s2_limb + subcc sz, 1, sz + be,pn %icc, .Lfinal_limb + clr carry + +.Lloop: + lduw [s1_ptr + 0x00], tmp1 + lduw [s1_ptr + 0x04], tmp2 + mulx tmp1, s2_limb, tmp3 + add s1_ptr, 8, s1_ptr + mulx tmp2, s2_limb, tmp4 + sub sz, 2, sz + add res_ptr, 8, res_ptr + add carry, tmp3, tmp3 + stw tmp3, [res_ptr - 0x08] + srlx tmp3, 32, carry + add carry, tmp4, tmp4 + stw tmp4, [res_ptr - 0x04] + brgz sz, .Lloop + srlx tmp4, 32, carry + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + lduw [s1_ptr + 0x00], tmp1 + mulx tmp1, s2_limb, tmp3 + add carry, tmp3, tmp3 + stw tmp3, [res_ptr + 0x00] + srlx tmp3, 32, carry + +.Lfinish: + retl + mov carry, %o0 +END(__mpn_mul_1) diff --git a/libc/sysdeps/sparc/sparc32/sparcv9/submul_1.S b/libc/sysdeps/sparc/sparc32/sparcv9/submul_1.S index de69533f6..8985e2a4c 100644 --- a/libc/sysdeps/sparc/sparc32/sparcv9/submul_1.S +++ b/libc/sysdeps/sparc/sparc32/sparcv9/submul_1.S @@ -1 +1,82 @@ -#include <sparcv8/submul_1.S> +! SPARC v9 32-bit __mpn_submul_1 -- Multiply a limb vector with a limb +! and subtract the result from a second limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz_arg %i2 +#define s2l_arg %i3 +#define sz %o4 +#define carry %o5 +#define s2_limb %g1 +#define tmp1 %l0 +#define tmp2 %l1 +#define tmp3 %l2 +#define tmp4 %l3 +#define tmp64_1 %g3 +#define tmp64_2 %o3 + +ENTRY(__mpn_submul_1) + save %sp, -96, %sp + srl sz_arg, 0, sz + srl s2l_arg, 0, s2_limb + subcc sz, 1, sz + be,pn %icc, .Lfinal_limb + subcc %g0, 0, carry + +.Lloop: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + lduw [s1_ptr + 0x04], tmp2 + lduw [res_ptr + 0x04], tmp4 + mulx tmp1, s2_limb, tmp64_1 + add s1_ptr, 8, s1_ptr + mulx tmp2, s2_limb, tmp64_2 + sub sz, 2, sz + add res_ptr, 8, res_ptr + addx carry, tmp64_1, tmp64_1 + srlx tmp64_1, 32, carry + subcc tmp3, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr - 0x08] + addx carry, tmp64_2, tmp64_2 + srlx tmp64_2, 32, carry + subcc tmp4, tmp64_2, tmp64_2 + brgz sz, .Lloop + stw tmp64_2, [res_ptr - 0x04] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + lduw [s1_ptr + 0x00], tmp1 + lduw [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp64_1 + addx carry, tmp64_1, tmp64_1 + srlx tmp64_1, 32, carry + subcc tmp3, tmp64_1, tmp64_1 + stw tmp64_1, [res_ptr + 0x00] + +.Lfinish: + addx carry, 0, carry + jmpl %i7 + 0x8, %g0 + restore carry, 0, %o0 +END(__mpn_submul_1) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/Makefile b/libc/sysdeps/sparc/sparc64/fpu/multiarch/Makefile index 83458484a..6a9274b4f 100644 --- a/libc/sysdeps/sparc/sparc64/fpu/multiarch/Makefile +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/Makefile @@ -1,4 +1,6 @@ ifeq ($(subdir),math) +libm-sysdep_routines += s_ceil-vis2 s_ceilf-vis2 \ + s_floor-vis2 s_floorf-vis2 ifeq ($(have-as-vis3),yes) libm-sysdep_routines += m_signbitf-vis3 m_signbit-vis3 s_ceilf-vis3 \ s_ceil-vis3 m_finitef-vis3 m_finite-vis3 \ @@ -7,7 +9,8 @@ libm-sysdep_routines += m_signbitf-vis3 m_signbit-vis3 s_ceilf-vis3 \ s_lrintf-vis3 s_lrint-vis3 s_rintf-vis3 \ s_rint-vis3 s_fminf-vis3 s_fmin-vis3 \ s_fmaxf-vis3 s_fmax-vis3 s_fmaf-vis3 \ - s_fma-vis3 + s_fma-vis3 s_nearbyint-vis3 s_nearbyintf-vis3 \ + s_truncf-vis3 s_trunc-vis3 sysdep_routines += s_signbitf-vis3 s_signbit-vis3 s_finitef-vis3 \ s_finite-vis3 s_isinff-vis3 s_isinf-vis3 \ s_isnanf-vis3 s_isnan-vis3 diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis2.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis2.S new file mode 100644 index 000000000..50d96a6ef --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis2.S @@ -0,0 +1,57 @@ +/* ceil function, sparc64 vis2 version. + Copyright (C) 2012-2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceil_vis2) + sethi %hi(TWO_FIFTYTWO), %o2 + fzero ZERO + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + stx %o2, [%sp + STACK_BIAS + 128] + fabsd %f0, %f14 + ldd [%sp + STACK_BIAS + 128], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 + faddd %f0, %f16, %f18 + siam (1 << 2) | 0 + fsubd %f18, %f16, %f18 + siam (0 << 2) + retl + for %f18, SIGN_BIT, %f0 +END (__ceil_vis2) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S index 9a598ea6f..6acff0999 100644 --- a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S @@ -19,57 +19,41 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_FIFTYTWO 0x43300000 /* 2**52 */ -#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__ceil_vis3) sethi %hi(TWO_FIFTYTWO), %o2 - sethi %hi(ONE_DOT_ZERO), %o3 fzero ZERO - sllx %o2, 32, %o2 fnegd ZERO, SIGN_BIT - - sllx %o3, 32, %o3 movxtod %o2, %f16 fabsd %f0, %f14 - fcmpd %fcc3, %f14, %f16 - fmovduge %fcc3, ZERO, %f16 fand %f0, SIGN_BIT, SIGN_BIT - for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 faddd %f0, %f16, %f18 + siam (1 << 2) | 0 fsubd %f18, %f16, %f18 - fcmpd %fcc2, %f18, %f0 - movxtod %o3, %f20 - - fmovduge %fcc2, ZERO, %f20 - faddd %f18, %f20, %f0 - fabsd %f0, %f0 + siam (0 << 2) retl - for %f0, SIGN_BIT, %f0 + for %f18, SIGN_BIT, %f0 END (__ceil_vis3) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S index fa4c7c353..e7822bc30 100644 --- a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S @@ -1,6 +1,6 @@ #include <sparc-ifunc.h> -SPARC_ASM_VIS3_IFUNC(ceil) +SPARC_ASM_VIS3_VIS2_IFUNC(ceil) weak_alias (__ceil, ceil) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis2.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis2.S new file mode 100644 index 000000000..cd5937b38 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis2.S @@ -0,0 +1,56 @@ +/* Float ceil function, sparc64 vis2 version. + Copyright (C) 2012-2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceilf_vis2) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + fnegs ZERO, SIGN_BIT + st %o2, [%sp + STACK_BIAS + 128] + fabss %f1, %f14 + ld [%sp + STACK_BIAS + 128], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 + fadds %f1, %f16, %f5 + siam (1 << 2) | 0 + fsubs %f5, %f16, %f5 + siam (0 << 2) + retl + fors %f5, SIGN_BIT, %f0 +END (__ceilf_vis2) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S index 8c635907d..b3ec3484d 100644 --- a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S @@ -19,55 +19,40 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ -#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__ceilf_vis3) sethi %hi(TWO_TWENTYTHREE), %o2 - sethi %hi(ONE_DOT_ZERO), %o3 fzeros ZERO - fnegs ZERO, SIGN_BIT - movwtos %o2, %f16 fabss %f1, %f14 - fcmps %fcc3, %f14, %f16 - fmovsuge %fcc3, ZERO, %f16 fands %f1, SIGN_BIT, SIGN_BIT - fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 2 fadds %f1, %f16, %f5 + siam (1 << 2) | 0 fsubs %f5, %f16, %f5 - fcmps %fcc2, %f5, %f1 - movwtos %o3, %f9 - - fmovsuge %fcc2, ZERO, %f9 - fadds %f5, %f9, %f0 - fabss %f0, %f0 + siam (0 << 2) retl - fors %f0, SIGN_BIT, %f0 + fors %f5, SIGN_BIT, %f0 END (__ceilf_vis3) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S index 3047dd8fa..1c72a5728 100644 --- a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S @@ -1,6 +1,6 @@ #include <sparc-ifunc.h> -SPARC_ASM_VIS3_IFUNC(ceilf) +SPARC_ASM_VIS3_VIS2_IFUNC(ceilf) weak_alias (__ceilf, ceilf) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis2.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis2.S new file mode 100644 index 000000000..5479ceddf --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis2.S @@ -0,0 +1,57 @@ +/* floor function, sparc64 vis2 version. + Copyright (C) 2012-2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floor_vis2) + sethi %hi(TWO_FIFTYTWO), %o2 + fzero ZERO + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + stx %o2, [%sp + STACK_BIAS + 128] + fabsd %f0, %f14 + ldd [%sp + STACK_BIAS + 128], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 + faddd %f0, %f16, %f18 + siam (1 << 2) | 0 + fsubd %f18, %f16, %f18 + siam (0 << 2) + retl + for %f18, SIGN_BIT, %f0 +END (__floor_vis2) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S index 169d20654..c2ffe9f41 100644 --- a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S @@ -19,57 +19,41 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_FIFTYTWO 0x43300000 /* 2**52 */ -#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__floor_vis3) sethi %hi(TWO_FIFTYTWO), %o2 - sethi %hi(ONE_DOT_ZERO), %o3 fzero ZERO - sllx %o2, 32, %o2 fnegd ZERO, SIGN_BIT - - sllx %o3, 32, %o3 movxtod %o2, %f16 fabsd %f0, %f14 - fcmpd %fcc3, %f14, %f16 - fmovduge %fcc3, ZERO, %f16 fand %f0, SIGN_BIT, SIGN_BIT - for %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 faddd %f0, %f16, %f18 + siam (1 << 2) | 0 fsubd %f18, %f16, %f18 - fcmpd %fcc2, %f18, %f0 - movxtod %o3, %f20 - - fmovdule %fcc2, ZERO, %f20 - fsubd %f18, %f20, %f0 - fabsd %f0, %f0 + siam (0 << 2) retl - for %f0, SIGN_BIT, %f0 + for %f18, SIGN_BIT, %f0 END (__floor_vis3) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S index 6ae9947a7..989ccab56 100644 --- a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S @@ -1,6 +1,6 @@ #include <sparc-ifunc.h> -SPARC_ASM_VIS3_IFUNC(floor) +SPARC_ASM_VIS3_VIS2_IFUNC(floor) weak_alias (__floor, floor) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis2.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis2.S new file mode 100644 index 000000000..935fa853d --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis2.S @@ -0,0 +1,56 @@ +/* Float floor function, sparc64 vis2 version. + Copyright (C) 2012-2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floorf_vis2) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + fnegs ZERO, SIGN_BIT + st %o2, [%sp + STACK_BIAS + 128] + fabss %f1, %f14 + ld [%sp + STACK_BIAS + 128], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 + fadds %f1, %f16, %f5 + siam (1 << 2) | 0 + fsubs %f5, %f16, %f5 + siam (0 << 2) + retl + fors %f5, SIGN_BIT, %f0 +END (__floorf_vis2) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S index 65be2977a..225e17ec0 100644 --- a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S @@ -19,55 +19,40 @@ #include <sysdep.h> - /* Since changing the rounding mode is extremely expensive, we - try to round up using a method that is rounding mode - agnostic. + /* 'siam' (Set Interval Arithmetic Mode) is used to quickly override + the rounding mode during this routine. We add then subtract (or subtract than add if the initial value was negative) 2**23 to the value, then subtract it back out. - This will clear out the fractional portion of the value. - One of two things will happen for non-whole initial values. - Either the rounding mode will round it up, or it will be - rounded down. If the value started out whole, it will be - equal after the addition and subtraction. This means we - can accurately detect with one test whether we need to add - another 1.0 to round it up properly. + This will clear out the fractional portion of the value and, + with suitable 'siam' initiated rouding mode settings, round + the final result in the proper direction. - VIS instructions are used to facilitate the formation of - easier constants, and the propagation of the sign bit. */ + We also use VIS3 moves to avoid using the stack to transfer + values between float and integer registers. */ #define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ -#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ #define ZERO %f10 /* 0.0 */ #define SIGN_BIT %f12 /* -0.0 */ ENTRY (__floorf_vis3) sethi %hi(TWO_TWENTYTHREE), %o2 - sethi %hi(ONE_DOT_ZERO), %o3 fzeros ZERO - fnegs ZERO, SIGN_BIT - - movwtos %o2, %f16 + movwtos %o2, %f16 fabss %f1, %f14 - fcmps %fcc3, %f14, %f16 - fmovsuge %fcc3, ZERO, %f16 fands %f1, SIGN_BIT, SIGN_BIT - fors %f16, SIGN_BIT, %f16 + siam (1 << 2) | 3 fadds %f1, %f16, %f5 + siam (1 << 2) | 0 fsubs %f5, %f16, %f5 - fcmps %fcc2, %f5, %f1 - movwtos %o3, %f9 - - fmovsule %fcc2, ZERO, %f9 - fsubs %f5, %f9, %f0 - fabss %f0, %f0 + siam (0 << 2) retl - fors %f0, SIGN_BIT, %f0 + fors %f5, SIGN_BIT, %f0 END (__floorf_vis3) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S index 31cda385b..d2a83cb9b 100644 --- a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S @@ -1,6 +1,6 @@ #include <sparc-ifunc.h> -SPARC_ASM_VIS3_IFUNC(floorf) +SPARC_ASM_VIS3_VIS2_IFUNC(floorf) weak_alias (__floorf, floorf) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S new file mode 100644 index 000000000..f2071d66c --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S @@ -0,0 +1,61 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc64 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint_vis3) + stx %fsr, [%sp + STACK_BIAS + 144] + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + ldx [%sp + STACK_BIAS + 144], %o4 + sethi %hi(0xf8003e0), %o5 + fzero ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegd ZERO, SIGN_BIT + andn %o4, %o5, %o4 + movxtod %o2, %f16 + stx %o4, [%sp + STACK_BIAS + 136] + ldx [%sp + STACK_BIAS + 136], %fsr + fabsd %f0, %f14 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ldx [%sp + STACK_BIAS + 144], %fsr +END (__nearbyint_vis3) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint.S new file mode 100644 index 000000000..bb75ab360 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyint.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(nearbyint) + +weak_alias (__nearbyint, nearbyint) + +# undef weak_alias +# define weak_alias(a, b) + +#define __nearbyint __nearbyint_generic + +#include "../s_nearbyint.S" diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S new file mode 100644 index 000000000..b08928f6f --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S @@ -0,0 +1,60 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc64 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf_vis3) + stx %fsr, [%sp + STACK_BIAS + 144] + sethi %hi(0xf8003e0), %o5 + sethi %hi(TWO_TWENTYTHREE), %o2 + ldx [%sp + STACK_BIAS + 144], %o4 + or %o5, %lo(0xf8003e0), %o5 + fzeros ZERO + andn %o4, %o5, %o4 + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + stx %o4, [%sp + STACK_BIAS + 136] + ldx [%sp + STACK_BIAS + 136], %fsr + fabss %f1, %f14 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ldx [%sp + STACK_BIAS + 144], %fsr +END (__nearbyintf_vis3) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf.S new file mode 100644 index 000000000..95100c1bf --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_nearbyintf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(nearbyintf) + +weak_alias (__nearbyintf, nearbyintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __nearbyintf __nearbyintf_generic + +#include "../s_nearbyintf.S" diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.S new file mode 100644 index 000000000..34ff42da8 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.S @@ -0,0 +1,53 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc64 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__trunc_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + fnegd ZERO, SIGN_BIT + movxtod %o2, %f16 + fabsd %f0, %f14 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f14 + fand %f0, SIGN_BIT, SIGN_BIT + fdtox %f14, %f14 + fxtod %f14, %f14 + faddd %f0, ZERO, %f18 + fmovduge %fcc3, %f18, %f14 + retl + for %f14, SIGN_BIT, %f0 +END (__trunc_vis3) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.S new file mode 100644 index 000000000..0d6f43a18 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(trunc) + +weak_alias (__trunc, trunc) + +# undef weak_alias +# define weak_alias(a, b) + +#define __trunc __trunc_generic + +#include "../s_trunc.S" diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.S new file mode 100644 index 000000000..e566b6ba8 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.S @@ -0,0 +1,52 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc64 vis3 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__truncf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + fnegs ZERO, SIGN_BIT + movwtos %o2,%f16 + fabss %f1, %f14 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f14 + fands %f1, SIGN_BIT, SIGN_BIT + fstoi %f14, %f14 + fitos %f14, %f14 + fadds %f1, ZERO, %f18 + fmovsuge %fcc3, %f18, %f14 + retl + fors %f14, SIGN_BIT, %f0 +END (__truncf_vis3) diff --git a/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.S b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.S new file mode 100644 index 000000000..2ca251733 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.S @@ -0,0 +1,12 @@ +#include <sparc-ifunc.h> + +SPARC_ASM_VIS3_IFUNC(truncf) + +weak_alias (__truncf, truncf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __truncf __truncf_generic + +#include "../s_truncf.S" diff --git a/libc/sysdeps/sparc/sparc64/fpu/s_fdim.S b/libc/sysdeps/sparc/sparc64/fpu/s_fdim.S new file mode 100644 index 000000000..a1c53dfb1 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/s_fdim.S @@ -0,0 +1,32 @@ +/* Compute positive difference, sparc 64-bit. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> +#include <math_ldbl_opt.h> + +ENTRY(__fdim) + fcmpd %f0, %f2 + fbug 1f + nop + fzero %f0 + fnegd %f0, %f2 +1: retl + fsubd %f0, %f2, %f0 +END(__fdim) +weak_alias (__fdim, fdim) diff --git a/libc/sysdeps/sparc/sparc64/fpu/s_fdimf.S b/libc/sysdeps/sparc/sparc64/fpu/s_fdimf.S new file mode 100644 index 000000000..61782a5f3 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/s_fdimf.S @@ -0,0 +1,31 @@ +/* Compute positive difference, sparc 64-bit. + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__fdimf) + fcmps %f1, %f3 + fbug 1f + nop + fzeros %f1 + fnegs %f1, %f3 +1: retl + fsubs %f1, %f3, %f0 +END(__fdimf) +weak_alias (__fdimf, fdimf) diff --git a/libc/sysdeps/sparc/sparc64/fpu/s_nearbyint.S b/libc/sysdeps/sparc/sparc64/fpu/s_nearbyint.S new file mode 100644 index 000000000..963e4bc7b --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/s_nearbyint.S @@ -0,0 +1,63 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc64 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyint) + stx %fsr, [%sp + STACK_BIAS + 144] + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + ldx [%sp + STACK_BIAS + 144], %o4 + sethi %hi(0xf8003e0), %o5 + fzero ZERO + or %o5, %lo(0xf8003e0), %o5 + fnegd ZERO, SIGN_BIT + andn %o4, %o5, %o4 + stx %o2, [%sp + STACK_BIAS + 128] + stx %o4, [%sp + STACK_BIAS + 136] + ldx [%sp + STACK_BIAS + 136], %fsr + fabsd %f0, %f14 + ldd [%sp + STACK_BIAS + 128], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + retl + ldx [%sp + STACK_BIAS + 144], %fsr +END (__nearbyint) +weak_alias (__nearbyint, nearbyint) diff --git a/libc/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S b/libc/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S new file mode 100644 index 000000000..4ff29058e --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/s_nearbyintf.S @@ -0,0 +1,62 @@ +/* Round float to int floating-point values without generating + an inexact exception, sparc64 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__nearbyintf) + stx %fsr, [%sp + STACK_BIAS + 144] + sethi %hi(0xf8003e0), %o5 + sethi %hi(TWO_TWENTYTHREE), %o2 + ldx [%sp + STACK_BIAS + 144], %o4 + or %o5, %lo(0xf8003e0), %o5 + fzeros ZERO + andn %o4, %o5, %o4 + fnegs ZERO, SIGN_BIT + st %o2, [%sp + STACK_BIAS + 128] + stx %o4, [%sp + STACK_BIAS + 136] + ldx [%sp + STACK_BIAS + 136], %fsr + fabss %f1, %f14 + ld [%sp + STACK_BIAS + 128], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + retl + ldx [%sp + STACK_BIAS + 144], %fsr +END (__nearbyintf) +weak_alias (__nearbyintf, nearbyintf) diff --git a/libc/sysdeps/sparc/sparc64/fpu/s_trunc.S b/libc/sysdeps/sparc/sparc64/fpu/s_trunc.S new file mode 100644 index 000000000..13d47eb97 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/s_trunc.S @@ -0,0 +1,55 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc64 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__trunc) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + fnegd ZERO, SIGN_BIT + stx %o2, [%sp + STACK_BIAS + 128] + fabsd %f0, %f14 + ldd [%sp + STACK_BIAS + 128], %f16 + fcmpd %fcc3, %f14, %f16 + fmovduge %fcc3, ZERO, %f14 + fand %f0, SIGN_BIT, SIGN_BIT + fdtox %f14, %f14 + fxtod %f14, %f14 + faddd %f0, ZERO, %f18 + fmovduge %fcc3, %f18, %f14 + retl + for %f14, SIGN_BIT, %f0 +END (__trunc) +weak_alias (__trunc, trunc) diff --git a/libc/sysdeps/sparc/sparc64/fpu/s_truncf.S b/libc/sysdeps/sparc/sparc64/fpu/s_truncf.S new file mode 100644 index 000000000..e25a1f595 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/fpu/s_truncf.S @@ -0,0 +1,54 @@ +/* Truncate argument to nearest integral value not larger than + the argument, sparc64 version. + + Copyright (C) 2013 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2013. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* We pop constants into the FPU registers using the incoming + argument stack slots, since this avoid having to use any PIC + references. We also thus avoid having to allocate a register + window. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__truncf) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + fnegs ZERO, SIGN_BIT + st %o2, [%sp + STACK_BIAS + 128] + fabss %f1, %f14 + ld [%sp + STACK_BIAS + 128], %f16 + fcmps %fcc3, %f14, %f16 + fmovsuge %fcc3, ZERO, %f14 + fands %f1, SIGN_BIT, SIGN_BIT + fstoi %f14, %f14 + fitos %f14, %f14 + fadds %f1, ZERO, %f18 + fmovsuge %fcc3, %f18, %f14 + retl + fors %f14, SIGN_BIT, %f0 +END (__truncf) +weak_alias (__truncf, truncf) diff --git a/libc/sysdeps/sparc/sparc64/multiarch/Makefile b/libc/sysdeps/sparc/sparc64/multiarch/Makefile index 4ad7aff91..55b757f9a 100644 --- a/libc/sysdeps/sparc/sparc64/multiarch/Makefile +++ b/libc/sysdeps/sparc/sparc64/multiarch/Makefile @@ -10,3 +10,12 @@ ifeq ($(subdir),string) sysdep_routines += memcpy-ultra3 memcpy-niagara1 memcpy-niagara2 \ memset-niagara1 memcpy-niagara4 memset-niagara4 endif + +ifeq ($(subdir),stdlib) +sysdep_routines += mul_1-vis3 addmul_1-vis3 submul_1-vis3 add_n-vis3 sub_n-vis3 +endif + +ifeq ($(subdir),math) +gmp-sysdep_routines = mul_1-vis3 addmul_1-vis3 submul_1-vis3 add_n-vis3 \ + sub_n-vis3 +endif diff --git a/libc/sysdeps/sparc/sparc64/multiarch/add_n-vis3.S b/libc/sysdeps/sparc/sparc64/multiarch/add_n-vis3.S new file mode 100644 index 000000000..185f31169 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/add_n-vis3.S @@ -0,0 +1,67 @@ +! SPARC v9 64-bit VIS3 __mpn_add_n -- Add two limb vectors of the same length > 0 and +! store sum in a third limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %o0 +#define s1_ptr %o1 +#define s2_ptr %o2 +#define sz %o3 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_add_n_vis3) + subcc sz, 1, sz + be .Lfinal_limb + cmp %g0, 0 + +.Lloop: + ldx [s2_ptr + 0x00], tmp1 + add s2_ptr, 0x10, s2_ptr + ldx [s1_ptr + 0x00], tmp2 + add s1_ptr, 0x10, s1_ptr + ldx [s2_ptr - 0x08], tmp3 + add res_ptr, 0x10, res_ptr + ldx [s1_ptr - 0x08], tmp4 + sub sz, 2, sz + addxccc tmp1, tmp2, tmp1 + stx tmp1, [res_ptr - 0x10] + addxccc tmp3, tmp4, tmp3 + brgz sz, .Lloop + stx tmp3, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s2_ptr + 0x00], tmp1 + ldx [s1_ptr + 0x00], tmp2 + addxccc tmp1, tmp2, tmp1 + stx tmp1, [res_ptr + 0x00] + +.Lfinish: + retl + addxc %g0, %g0, %o0 +END(__mpn_add_n_vis3) diff --git a/libc/sysdeps/sparc/sparc64/multiarch/add_n.S b/libc/sysdeps/sparc/sparc64/multiarch/add_n.S new file mode 100644 index 000000000..25cae3977 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/add_n.S @@ -0,0 +1,56 @@ +/* Multiple versions of add_n + + Copyright (C) 2013 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_add_n) + .type __mpn_add_n, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_add_n_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_add_n_vis3), %o1 +# else + set __mpn_add_n_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_add_n_generic), %o1 + xor %o1, %gdop_lox10(__mpn_add_n_generic), %o1 +# else + set __mpn_add_n_vis3, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_add_n) + +#define __mpn_add_n __mpn_add_n_generic +#include "../add_n.S" diff --git a/libc/sysdeps/sparc/sparc64/multiarch/addmul_1-vis3.S b/libc/sysdeps/sparc/sparc64/multiarch/addmul_1-vis3.S new file mode 100644 index 000000000..f955b27c0 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/addmul_1-vis3.S @@ -0,0 +1,87 @@ +! SPARC v9 64-bit VIS3 __mpn_addmul_1 -- Multiply a limb vector with a +! limb and add the result to a second limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz %i2 +#define s2_limb %i3 +#define carry %o5 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 +#define tmp5 %l0 +#define tmp6 %l1 +#define tmp7 %l2 +#define tmp8 %l3 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_addmul_1_vis3) + save %sp, -176, %sp + subcc sz, 1, sz + be .Lfinal_limb + clr carry + +.Lloop: + ldx [s1_ptr + 0x00], tmp1 + ldx [res_ptr + 0x00], tmp3 + ldx [s1_ptr + 0x08], tmp2 + ldx [res_ptr + 0x08], tmp4 + mulx tmp1, s2_limb, tmp5 + add s1_ptr, 0x10, s1_ptr + umulxhi tmp1, s2_limb, tmp6 + add res_ptr, 0x10, res_ptr + mulx tmp2, s2_limb, tmp7 + sub sz, 2, sz + umulxhi tmp2, s2_limb, tmp8 + addcc carry, tmp5, tmp5 + addxc %g0, tmp6, carry + addcc tmp3, tmp5, tmp5 + addxc %g0, carry, carry + stx tmp5, [res_ptr - 0x10] + addcc carry, tmp7, tmp7 + addxc %g0, tmp8, carry + addcc tmp4, tmp7, tmp7 + addxc %g0, carry, carry + brgz sz, .Lloop + stx tmp7, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s1_ptr + 0x00], tmp1 + ldx [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp5 + umulxhi tmp1, s2_limb, tmp6 + addcc carry, tmp5, tmp5 + addxc %g0, tmp6, carry + addcc tmp3, tmp5, tmp5 + addxc %g0, carry, carry + stx tmp5, [res_ptr + 0x00] + +.Lfinish: + jmpl %i7 + 8, %g0 + restore carry, 0, %o0 +END(__mpn_addmul_1_vis3) diff --git a/libc/sysdeps/sparc/sparc64/multiarch/addmul_1.S b/libc/sysdeps/sparc/sparc64/multiarch/addmul_1.S new file mode 100644 index 000000000..a1659e40e --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/addmul_1.S @@ -0,0 +1,56 @@ +/* Multiple versions of addmul_1 + + Copyright (C) 2013 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_addmul_1) + .type __mpn_addmul_1, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_addmul_1_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_addmul_1_vis3), %o1 +# else + set __mpn_addmul_1_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_addmul_1_generic), %o1 + xor %o1, %gdop_lox10(__mpn_addmul_1_generic), %o1 +# else + set __mpn_addmul_1_vis3, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_addmul_1) + +#define __mpn_addmul_1 __mpn_addmul_1_generic +#include "../addmul_1.S" diff --git a/libc/sysdeps/sparc/sparc64/multiarch/mul_1-vis3.S b/libc/sysdeps/sparc/sparc64/multiarch/mul_1-vis3.S new file mode 100644 index 000000000..61fbe27a4 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/mul_1-vis3.S @@ -0,0 +1,73 @@ +! SPARC v9 64-bit VIS3 __mpn_mul_1 -- Multiply a limb vector with a single +! limb and store the product in a second limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %o0 +#define s1_ptr %o1 +#define sz %o2 +#define s2_limb %o3 +#define carry %o5 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_mul_1_vis3) + subcc sz, 1, sz + be .Lfinal_limb + clr carry + +.Lloop: + ldx [s1_ptr + 0x00], tmp1 + ldx [s1_ptr + 0x08], tmp4 + mulx tmp1, s2_limb, tmp3 + add s1_ptr, 0x10, s1_ptr + umulxhi tmp1, s2_limb, tmp2 + sub sz, 2, sz + mulx tmp4, s2_limb, tmp1 + add res_ptr, 0x10, res_ptr + umulxhi tmp4, s2_limb, tmp4 + addcc carry, tmp3, tmp3 + stx tmp3, [res_ptr - 0x10] + addxc %g0, tmp2, carry + addcc carry, tmp1, tmp1 + addxc %g0, tmp4, carry + brgz sz, .Lloop + stx tmp1, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s1_ptr + 0x00], tmp1 + mulx tmp1, s2_limb, tmp3 + umulxhi tmp1, s2_limb, tmp2 + addcc carry, tmp3, tmp3 + addxc %g0, tmp2, carry + stx tmp3, [res_ptr + 0x00] + +.Lfinish: + retl + mov carry, %o0 +END(__mpn_mul_1_vis3) diff --git a/libc/sysdeps/sparc/sparc64/multiarch/mul_1.S b/libc/sysdeps/sparc/sparc64/multiarch/mul_1.S new file mode 100644 index 000000000..25f51bf81 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/mul_1.S @@ -0,0 +1,56 @@ +/* Multiple versions of mul_1 + + Copyright (C) 2013 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_mul_1) + .type __mpn_mul_1, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_mul_1_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_mul_1_vis3), %o1 +# else + set __mpn_mul_1_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_mul_1_generic), %o1 + xor %o1, %gdop_lox10(__mpn_mul_1_generic), %o1 +# else + set __mpn_mul_1_vis3, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_mul_1) + +#define __mpn_mul_1 __mpn_mul_1_generic +#include "../mul_1.S" diff --git a/libc/sysdeps/sparc/sparc64/multiarch/sub_n-vis3.S b/libc/sysdeps/sparc/sparc64/multiarch/sub_n-vis3.S new file mode 100644 index 000000000..4e9a786d3 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/sub_n-vis3.S @@ -0,0 +1,71 @@ +! SPARC v9 64-bit VIS3 __mpn_sub_n -- Subtract two limb vectors of the same length > 0 +! and store difference in a third limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %o0 +#define s1_ptr %o1 +#define s2_ptr %o2 +#define sz %o3 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_sub_n_vis3) + subcc sz, 1, sz + be .Lfinal_limb + cmp %g0, 1 + +.Lloop: + ldx [s2_ptr + 0x00], tmp1 + add s2_ptr, 0x10, s2_ptr + ldx [s1_ptr + 0x00], tmp2 + add s1_ptr, 0x10, s1_ptr + ldx [s2_ptr - 0x08], tmp3 + add res_ptr, 0x10, res_ptr + ldx [s1_ptr - 0x08], tmp4 + sub sz, 2, sz + xnor tmp1, %g0, tmp1 + addxccc tmp1, tmp2, tmp1 + stx tmp1, [res_ptr - 0x10] + xnor tmp3, %g0, tmp3 + addxccc tmp3, tmp4, tmp3 + brgz sz, .Lloop + stx tmp3, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s2_ptr + 0x00], tmp1 + ldx [s1_ptr + 0x00], tmp2 + xnor tmp1, %g0, tmp1 + addxccc tmp1, tmp2, tmp1 + stx tmp1, [res_ptr + 0x00] + +.Lfinish: + clr %o0 + retl + movcc %xcc, 1, %o0 +END(__mpn_sub_n_vis3) diff --git a/libc/sysdeps/sparc/sparc64/multiarch/sub_n.S b/libc/sysdeps/sparc/sparc64/multiarch/sub_n.S new file mode 100644 index 000000000..5e15bea10 --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/sub_n.S @@ -0,0 +1,56 @@ +/* Multiple versions of sub_n + + Copyright (C) 2013 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_sub_n) + .type __mpn_sub_n, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_sub_n_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_sub_n_vis3), %o1 +# else + set __mpn_sub_n_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_sub_n_generic), %o1 + xor %o1, %gdop_lox10(__mpn_sub_n_generic), %o1 +# else + set __mpn_sub_n_vis3, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_sub_n) + +#define __mpn_sub_n __mpn_sub_n_generic +#include "../sub_n.S" diff --git a/libc/sysdeps/sparc/sparc64/multiarch/submul_1-vis3.S b/libc/sysdeps/sparc/sparc64/multiarch/submul_1-vis3.S new file mode 100644 index 000000000..8f10f918a --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/submul_1-vis3.S @@ -0,0 +1,87 @@ +! SPARC v9 64-bit VIS3 __mpn_submul_1 -- Multiply a limb vector with a +! limb and subtract the result from a second limb vector. +! +! Copyright (C) 2013 Free Software Foundation, Inc. +! This file is part of the GNU C Library. +! Contributed by David S. Miller <davem@davemloft.net> +! +! The GNU C Library is free software; you can redistribute it and/or +! modify it under the terms of the GNU Lesser General Public +! License as published by the Free Software Foundation; either +! version 2.1 of the License, or (at your option) any later version. +! +! The GNU C Library is distributed in the hope that it will be useful, +! but WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! Lesser General Public License for more details. +! +! You should have received a copy of the GNU Lesser General Public +! License along with the GNU C Library; if not, see +! <http://www.gnu.org/licenses/>. + +#include <sysdep.h> + +#define res_ptr %i0 +#define s1_ptr %i1 +#define sz %i2 +#define s2_limb %i3 +#define carry %o5 +#define tmp1 %g1 +#define tmp2 %g2 +#define tmp3 %g3 +#define tmp4 %o4 +#define tmp5 %l0 +#define tmp6 %l1 +#define tmp7 %l2 +#define tmp8 %l3 + + .register %g2,#scratch + .register %g3,#scratch +ENTRY(__mpn_submul_1_vis3) + save %sp, -176, %sp + subcc sz, 1, sz + be .Lfinal_limb + clr carry + +.Lloop: + ldx [s1_ptr + 0x00], tmp1 + ldx [res_ptr + 0x00], tmp3 + ldx [s1_ptr + 0x08], tmp2 + ldx [res_ptr + 0x08], tmp4 + mulx tmp1, s2_limb, tmp5 + add s1_ptr, 0x10, s1_ptr + umulxhi tmp1, s2_limb, tmp6 + add res_ptr, 0x10, res_ptr + mulx tmp2, s2_limb, tmp7 + sub sz, 2, sz + umulxhi tmp2, s2_limb, tmp8 + addcc carry, tmp5, tmp5 + addxc %g0, tmp6, carry + subcc tmp3, tmp5, tmp5 + addxc %g0, carry, carry + stx tmp5, [res_ptr - 0x10] + addcc carry, tmp7, tmp7 + addxc %g0, tmp8, carry + subcc tmp4, tmp7, tmp7 + addxc %g0, carry, carry + brgz sz, .Lloop + stx tmp7, [res_ptr - 0x08] + + brlz,pt sz, .Lfinish + nop + +.Lfinal_limb: + ldx [s1_ptr + 0x00], tmp1 + ldx [res_ptr + 0x00], tmp3 + mulx tmp1, s2_limb, tmp5 + umulxhi tmp1, s2_limb, tmp6 + addcc carry, tmp5, tmp5 + addxc %g0, tmp6, carry + subcc tmp3, tmp5, tmp5 + addxc %g0, carry, carry + stx tmp5, [res_ptr + 0x00] + +.Lfinish: + jmpl %i7 + 8, %g0 + restore carry, 0, %o0 +END(__mpn_submul_1_vis3) diff --git a/libc/sysdeps/sparc/sparc64/multiarch/submul_1.S b/libc/sysdeps/sparc/sparc64/multiarch/submul_1.S new file mode 100644 index 000000000..68552e9af --- /dev/null +++ b/libc/sysdeps/sparc/sparc64/multiarch/submul_1.S @@ -0,0 +1,56 @@ +/* Multiple versions of submul_1 + + Copyright (C) 2013 Free Software Foundation, Inc. + Contributed by David S. Miller (davem@davemloft.net) + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY(__mpn_submul_1) + .type __mpn_submul_1, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 1f + nop +# ifdef SHARED + sethi %gdop_hix22(__mpn_submul_1_vis3), %o1 + xor %o1, %gdop_lox10(__mpn_submul_1_vis3), %o1 +# else + set __mpn_submul_1_vis3, %o1 +# endif + ba 10f + nop +1: +# ifdef SHARED + sethi %gdop_hix22(__mpn_submul_1_generic), %o1 + xor %o1, %gdop_lox10(__mpn_submul_1_generic), %o1 +# else + set __mpn_submul_1_vis3, %o1 +# endif +10: +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__mpn_submul_1) + +#define __mpn_submul_1 __mpn_submul_1_generic +#include "../submul_1.S" |