diff options
author | John Högberg <john@erlang.org> | 2023-01-29 22:06:52 +0100 |
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committer | John Högberg <john@erlang.org> | 2023-02-01 10:37:19 +0100 |
commit | 88bdc65784ed731610b5a30de421d97c33c8111b (patch) | |
tree | 1395d3ae7a5e160d97e25d93120c19ca7e718fdd /erts/configure | |
parent | 614a3f2a4a43b1e98cd6b11330ddcfd7ae69fc92 (diff) | |
download | erlang-88bdc65784ed731610b5a30de421d97c33c8111b.tar.gz |
jit: Clear instruction cache ourselves
`__builtin__clear_cache` issues full memory and instruction
barriers in addition to clearing the cache. This is bad because it
may hide bugs where we've failed to issue barriers on all
schedulers before executing code.
If we clear the cache ourselves without issuing these barriers,
we'll crash really quick if we forget to issue them for all
schedulers later on.
Diffstat (limited to 'erts/configure')
-rwxr-xr-x | erts/configure | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/erts/configure b/erts/configure index c8f5ad0e78..27b889e370 100755 --- a/erts/configure +++ b/erts/configure @@ -13990,6 +13990,77 @@ printf "%s\n" "$ethr_cv_arm_isb_sy_instr" >&6; } if test $ethr_cv_arm_isb_sy_instr = yes; then ethr_arm_isb_sy_instr_val=1 fi + + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'dc cvau' instruction" >&5 +printf %s "checking for ARM 'dc cvau' instruction... " >&6; } +if test ${ethr_cv_arm_dc_cvau_instr+y} +then : + printf %s "(cached) " >&6 +else $as_nop + + ethr_cv_arm_dc_cvau_instr=no + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main (void) +{ + char data[512]; + __asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory"); + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO" +then : + ethr_cv_arm_dc_cvau_instr=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.beam \ + conftest$ac_exeext conftest.$ac_ext + +fi +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ethr_cv_arm_dc_cvau_instr" >&5 +printf "%s\n" "$ethr_cv_arm_dc_cvau_instr" >&6; } + if test $ethr_cv_arm_dc_cvau_instr = yes; then + ethr_arm_dc_cvau_instr_val=1 + fi + + { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for ARM 'ic ivau' instruction" >&5 +printf %s "checking for ARM 'ic ivau' instruction... " >&6; } +if test ${ethr_cv_arm_ic_ivau_instr+y} +then : + printf %s "(cached) " >&6 +else $as_nop + + ethr_cv_arm_ic_ivau_instr=no + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main (void) +{ + char data[512]; + __asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory"); + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO" +then : + ethr_cv_arm_ic_ivau_instr=yes +fi +rm -f core conftest.err conftest.$ac_objext conftest.beam \ + conftest$ac_exeext conftest.$ac_ext + +fi +{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ethr_cv_arm_ic_ivau_instr" >&5 +printf "%s\n" "$ethr_cv_arm_ic_ivau_instr" >&6; } + if test $ethr_cv_arm_ic_ivau_instr = yes; then + ethr_arm_dc_cvau_instr_val=1 + fi + ;; #( *) : ;; @@ -14008,6 +14079,13 @@ printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_DMB_LD_INSTRUCTION $ethr_arm_dbm_ld printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_ISB_SY_INSTRUCTION $ethr_arm_isb_sy_instr_val" >>confdefs.h +printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION $ethr_arm_dc_cvau_instr_val" >>confdefs.h + + +printf "%s\n" "#define ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION $ethr_arm_ic_ivau_instr_val" >>confdefs.h + + + test $ethr_cv_32bit___sync_val_compare_and_swap = yes && ethr_have_gcc_native_atomics=yes test $ethr_cv_64bit___sync_val_compare_and_swap = yes && |