Merge branch 'maint'

* maint:
  Enable __atomic aquire/release barriers for Apple's clang as of v12.0.0
  Improve memory barrier usage for ARMv8
  Remove unnecessary data dependency read barrier on 64-bit ARM

3 files changed, 74 insertions, 8 deletions

diff --git a/erts/include/internal/ethread_header_config.h.in b/erts/include/internal/ethread_header_config.h.in
index 6309f10439..80ec4dd864 100644
--- a/erts/include/internal/ethread_header_config.h.in
+++ b/erts/include/internal/ethread_header_config.h.in
@@ -86,10 +86,20 @@
 #undef ETHR_SPARC_RMO
 
 /* Define as a boolean indicating whether you have a gcc compatible compiler
-   capable of generating the ARM DMB instruction, and are compiling for an ARM
-   processor with ARM DMB instruction support, or not */
+   capable of generating the ARM 'dmb sy' instruction, and are compiling for
+   an ARM processor with ARM DMB instruction support, or not */
 #undef ETHR_HAVE_GCC_ASM_ARM_DMB_INSTRUCTION
 
+/* Define as a boolean indicating whether you have a gcc compatible compiler
+   capable of generating the ARM 'dmb ld' instruction, and are compiling for
+   an ARM processor with ARM DMB instruction support, or not */
+#undef ETHR_HAVE_GCC_ASM_ARM_DMB_LD_INSTRUCTION
+
+/* Define as a boolean indicating whether you have a gcc compatible compiler
+   capable of generating the ARM 'dmb st' instruction, and are compiling for
+   an ARM processor with ARM DMB instruction support, or not */
+#undef ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION
+
 /* Define as a bitmask corresponding to the word sizes that
    __sync_synchronize() can handle on your system */
 #undef ETHR_HAVE___sync_synchronize
diff --git a/erts/include/internal/gcc/ethr_membar.h b/erts/include/internal/gcc/ethr_membar.h
index 643b243683..4e1eb1117e 100644
--- a/erts/include/internal/gcc/ethr_membar.h
+++ b/erts/include/internal/gcc/ethr_membar.h
@@ -149,14 +149,51 @@ ethr_full_fence__(void)
     __asm__ __volatile__("dmb sy" : : : "memory");
 }
 
+#if ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION
 static __inline__ __attribute__((__always_inline__)) void
 ethr_store_fence__(void)
 {
+    /* StoreStore */
     __asm__ __volatile__("dmb st" : : : "memory");
 }
+#endif
+
+#if ETHR_HAVE_GCC_ASM_ARM_DMB_LD_INSTRUCTION
+static __inline__ __attribute__((__always_inline__)) void
+ethr_load_fence__(void)
+{
+    /* LoadLoad and LoadStore */
+    __asm__ __volatile__("dmb ld" : : : "memory");
+}
+#endif
 
-#define ETHR_MEMBAR(B) \
- ETHR_CHOOSE_EXPR((B) == ETHR_StoreStore, ethr_store_fence__(), ethr_full_fence__())
+#if ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION && ETHR_HAVE_GCC_ASM_ARM_DMB_LD_INSTRUCTION
+/* sy, st & ld */
+#define ETHR_MEMBAR(B)                                                  \
+    ETHR_CHOOSE_EXPR((B) == ETHR_StoreStore,                            \
+                     ethr_store_fence__(),                              \
+                     ETHR_CHOOSE_EXPR((B) & (ETHR_StoreStore            \
+                                             | ETHR_StoreLoad),         \
+                                      ethr_full_fence__(),              \
+                                      ethr_load_fence__()))
+#elif ETHR_HAVE_GCC_ASM_ARM_DMB_ST_INSTRUCTION
+/* sy & st */
+#define ETHR_MEMBAR(B)                                                  \
+    ETHR_CHOOSE_EXPR((B) == ETHR_StoreStore,                            \
+                     ethr_store_fence__(), \
+                     ethr_full_fence__())
+#elif ETHR_HAVE_GCC_ASM_ARM_DMB_LD_INSTRUCTION
+/* sy & ld */
+#define ETHR_MEMBAR(B)                                                  \
+    ETHR_CHOOSE_EXPR((B) & (ETHR_StoreStore                             \
+                            | ETHR_StoreLoad),                          \
+                     ethr_full_fence__(),                               \
+                     ethr_load_fence__())
+#else
+/* sy */
+#define ETHR_MEMBAR(B)                                                  \
+ ethr_full_fence__()
+#endif
 
 #elif ETHR_HAVE___sync_synchronize
 
@@ -205,9 +242,12 @@ ethr_full_fence__(void)
 /*
  * Define ETHR_READ_DEPEND_MEMORY_BARRIER for all architechtures
  * not known to order data dependent loads
+ *
+ * This is a bit too conservative, but better safe than sorry...
+ * Add more archs as needed...
  */
 
-#if !defined(__ia64__) && !defined(__arm__)
+#if !defined(__ia64__) && !defined(__arm__) && !defined(__arm64__)
 #  define ETHR_READ_DEPEND_MEMORY_BARRIER ETHR_MEMBAR(ETHR_LoadLoad)
 #endif
 
diff --git a/erts/include/internal/gcc/ethread.h b/erts/include/internal/gcc/ethread.h
index 12b41f8704..0fb24445d0 100644
--- a/erts/include/internal/gcc/ethread.h
+++ b/erts/include/internal/gcc/ethread.h
@@ -44,6 +44,10 @@
 #undef ETHR_GCC_RELB_VERSIONS__
 #undef ETHR_GCC_RELB_MOD_VERSIONS__
 #undef ETHR_GCC_MB_MOD_VERSIONS__
+#undef ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS__
+
+#define ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS__ \
+    ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS
 
 /*
  * True GNU GCCs before version 4.8 do not emit a memory barrier
@@ -52,15 +56,27 @@
  */
 #undef ETHR___atomic_load_ACQUIRE_barrier_bug
 #if ETHR_GCC_COMPILER != ETHR_GCC_COMPILER_TRUE
+     
+#if ETHR_GCC_COMPILER == ETHR_GCC_COMPILER_CLANG \
+    && defined(__apple_build_version__)          \
+    && __clang_major__ >= 12
+/* Apples clang verified not to have this bug */
+#    define ETHR___atomic_load_ACQUIRE_barrier_bug 0
+/* Also trust builtin barriers */
+#    undef ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS__
+#    define ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS__ 1
+#  else
 /*
- * A gcc compatible compiler. We have no information
+ * Another gcc compatible compiler. We have no information
  * about the existence of this bug, but we assume
  * that it is not impossible that it could have
  * been "inherited". Therefore, until we are certain
  * that the bug does not exist, we assume that it
  * does.
  */
-#  define ETHR___atomic_load_ACQUIRE_barrier_bug ETHR_GCC_VERSIONS_MASK__
+#    define ETHR___atomic_load_ACQUIRE_barrier_bug ETHR_GCC_VERSIONS_MASK__
+#  endif
+
 #elif !ETHR_AT_LEAST_GCC_VSN__(4, 8, 0)
 /* True gcc of version < 4.8, i.e., bug exist... */
 #  define ETHR___atomic_load_ACQUIRE_barrier_bug ETHR_GCC_VERSIONS_MASK__
@@ -87,7 +103,7 @@
 #define ETHR_GCC_RELAXED_VERSIONS__ ETHR_GCC_VERSIONS_MASK__
 #define ETHR_GCC_RELAXED_MOD_VERSIONS__ ETHR_GCC_VERSIONS_MASK__
 
-#if ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS
+#if ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS__
 #  define ETHR_GCC_ACQB_VERSIONS__ ETHR_GCC_VERSIONS_MASK__
 #  define ETHR_GCC_ACQB_MOD_VERSIONS__ ETHR_GCC_VERSIONS_MASK__
 #  define ETHR_GCC_RELB_VERSIONS__ ETHR_GCC_VERSIONS_MASK__