diff options
| author | Rémi Denis-Courmont <remi@remlab.net> | 2022-09-26 17:52:38 +0300 |
|---|---|---|
| committer | Lynne <dev@lynne.ee> | 2022-09-27 13:19:52 +0200 |
| commit | cd77662953942cf166f0115b21cb8619e2e8f630 (patch) | |
| tree | 48fc82c466502ad52a5c4de04d0dedd5a0b18be2 /libavutil/riscv | |
| parent | b493370662eaa87f84450e876b8b61b34d91f23d (diff) | |
| download | ffmpeg-cd77662953942cf166f0115b21cb8619e2e8f630.tar.gz | |
lavu/floatdsp: RISC-V V scalarproduct_float
Diffstat (limited to 'libavutil/riscv')
| -rw-r--r-- | libavutil/riscv/float_dsp_init.c | 2 | ||||
| -rw-r--r-- | libavutil/riscv/float_dsp_rvv.S | 20 |
2 files changed, 22 insertions, 0 deletions
diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c index 44a505308d..e61f887862 100644 --- a/libavutil/riscv/float_dsp_init.c +++ b/libavutil/riscv/float_dsp_init.c @@ -38,6 +38,7 @@ void ff_vector_fmul_add_rvv(float *dst, const float *src0, const float *src1, void ff_vector_fmul_reverse_rvv(float *dst, const float *src0, const float *src1, int len); void ff_butterflies_float_rvv(float *v1, float *v2, int len); +float ff_scalarproduct_float_rvv(const float *v1, const float *v2, int len); void ff_vector_dmul_rvv(double *dst, const double *src0, const double *src1, int len); @@ -59,6 +60,7 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp) fdsp->vector_fmul_add = ff_vector_fmul_add_rvv; fdsp->vector_fmul_reverse = ff_vector_fmul_reverse_rvv; fdsp->butterflies_float = ff_butterflies_float_rvv; + fdsp->scalarproduct_float = ff_scalarproduct_float_rvv; } if (flags & AV_CPU_FLAG_RVV_F64) { diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S index ce530f6108..ab2e0c42d7 100644 --- a/libavutil/riscv/float_dsp_rvv.S +++ b/libavutil/riscv/float_dsp_rvv.S @@ -165,6 +165,26 @@ func ff_butterflies_float_rvv, zve32f ret endfunc +// a0 = (a0).(a1) [0..a2-1] +func ff_scalarproduct_float_rvv, zve32f + vsetvli zero, zero, e32, m1, ta, ma + vmv.s.x v8, zero +1: + vsetvli t0, a2, e32, m1, ta, ma + vle32.v v16, (a0) + sub a2, a2, t0 + vle32.v v24, (a1) + sh2add a0, t0, a0 + vfmul.vv v16, v16, v24 + sh2add a1, t0, a1 + vfredusum.vs v8, v16, v8 + bnez a2, 1b + + vfmv.f.s fa0, v8 +NOHWF fmv.x.w a0, fa0 + ret +endfunc + // (a0) = (a1) * (a2) [0..a3-1] func ff_vector_dmul_rvv, zve64d 1: |