par_masters: Reshuffle to remove forward declarations

Dispense with all these forward declarations by way of
ordering. Just deal with all the par_masters in one go
to be over and done with.

BUG=none
BRANCH=none
TEST=builds

Change-Id: I88e89992380195fee7c9de7ec57502ab980ec5df
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 28 insertions, 32 deletions

diff --git a/nicnatsemi.c b/nicnatsemi.c
index 77b54407..56297fe4 100644
--- a/nicnatsemi.c
+++ b/nicnatsemi.c
@@ -35,9 +35,35 @@ const struct dev_entry nics_natsemi[] = {
 };
 
 static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
-				   chipaddr addr);
+				   chipaddr addr)
+{
+	OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);
+	/*
+	 * The datasheet requires 32 bit accesses to this register, but it seems
+	 * that requirement might only apply if the register is memory mapped.
+	 * Bits 8-31 of this register are apparently don't care, and if this
+	 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
+	 * register seem to work fine. Due to that, we ignore the advice in the
+	 * data sheet.
+	 */
+	OUTB(val, io_base_addr + BOOT_ROM_DATA);
+}
+
 static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
-				     const chipaddr addr);
+				     const chipaddr addr)
+{
+	OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
+	/*
+	 * The datasheet requires 32 bit accesses to this register, but it seems
+	 * that requirement might only apply if the register is memory mapped.
+	 * Bits 8-31 of this register are apparently don't care, and if this
+	 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
+	 * register seem to work fine. Due to that, we ignore the advice in the
+	 * data sheet.
+	 */
+	return INB(io_base_addr + BOOT_ROM_DATA);
+}
+
 static const struct par_master par_master_nicnatsemi = {
 		.chip_readb		= nicnatsemi_chip_readb,
 		.chip_readw		= fallback_chip_readw,
@@ -76,36 +102,6 @@ int nicnatsemi_init(void)
 	return 0;
 }
 
-static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
-				   chipaddr addr)
-{
-	OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);
-	/*
-	 * The datasheet requires 32 bit accesses to this register, but it seems
-	 * that requirement might only apply if the register is memory mapped.
-	 * Bits 8-31 of this register are apparently don't care, and if this
-	 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
-	 * register seem to work fine. Due to that, we ignore the advice in the
-	 * data sheet.
-	 */
-	OUTB(val, io_base_addr + BOOT_ROM_DATA);
-}
-
-static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
-				     const chipaddr addr)
-{
-	OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
-	/*
-	 * The datasheet requires 32 bit accesses to this register, but it seems
-	 * that requirement might only apply if the register is memory mapped.
-	 * Bits 8-31 of this register are apparently don't care, and if this
-	 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
-	 * register seem to work fine. Due to that, we ignore the advice in the
-	 * data sheet.
-	 */
-	return INB(io_base_addr + BOOT_ROM_DATA);
-}
-
 #else
 #error PCI port I/O access is not supported on this architecture yet.
 #endif