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| author | Nicholas Chin <nic.c3.14@gmail.com> | 2022-10-23 13:10:31 -0600 |
|---|---|---|
| committer | Thomas Heijligen <src@posteo.de> | 2023-02-27 10:13:01 +0000 |
| commit | 0facf12ca413adbe803c819f55938e41c440dde5 (patch) | |
| tree | bda1308afa5f96369d99f0720ab2d5a75c0ccc17 /programmer_table.c | |
| parent | 83b051a9b4080382bef1c1b3366b2c4d3b52b979 (diff) | |
| download | flashrom-git-0facf12ca413adbe803c819f55938e41c440dde5.tar.gz | |
ch347_spi: Add initial support for the WCH CH347
Add support for the WCH CH347, a high-speed USB to bus converter
supporting multiple protocols interfaces including SPI. Currently only
mode 1 (vendor defined communication interface) is supported, mode 2
(USB HID communication interface) support will be added later. The code
is currently hard coded to use CS1 and a SPI clock of 15 MHz, though
there are 2 CS lines and 6 other GPIO lines available, as well as a
configurable clock divisor for up to 60MHz operation. Support for these
will be exposed through programmer parameters in later commits.
This currently uses the synchronous libusb API. Performance seems to be
alright so far, if it becomes an issue I may switch to the asynchronous
API.
Tested with a MX25L1606E flash chip
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba
Reviewed-on: https://review.coreboot.org/c/flashrom/+/70573
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'programmer_table.c')
| -rw-r--r-- | programmer_table.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/programmer_table.c b/programmer_table.c index 09351679..79acd779 100644 --- a/programmer_table.c +++ b/programmer_table.c @@ -156,6 +156,10 @@ const struct programmer_entry *const programmer_table[] = { &programmer_ch341a_spi, #endif +#if CONFIG_CH347_SPI == 1 + &programmer_ch347_spi, +#endif + #if CONFIG_DIGILENT_SPI == 1 &programmer_digilent_spi, #endif |