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author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2014-08-08 08:33:01 +0000 |
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committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2014-08-08 08:33:01 +0000 |
commit | f69f0c63b93e60c9c3bfd2cb6f88544479ce2918 (patch) | |
tree | 64ff1e62b06ee89492c914e11c86b54ddf126b0c /82802ab.c | |
parent | a38e1e165c826e968ef144dcc74da6a3358097a6 (diff) | |
download | flashrom-f69f0c63b93e60c9c3bfd2cb6f88544479ce2918.tar.gz |
Unify non-shifted and shifted JEDEC access.
Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use
normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit)
for 8-bit mode. Some programmers can access them in 16-bit mode, but on
all flashrom-supported programmers so far, we access them in 8-bit mode.
This means we have to shift the addresses but apart from the addresses
we can share the code.
This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED
flag in common JEDEC functions and applying the right addresses respectively.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to '82802ab.c')
-rw-r--r-- | 82802ab.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -44,7 +44,7 @@ int probe_82802ab(struct flashctx *flash) { chipaddr bios = flash->virtual_memory; uint8_t id1, id2, flashcontent1, flashcontent2; - int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) != 0; + int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; /* Reset to get a clean state */ chip_writeb(flash, 0xFF, bios); |