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| author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-05-04 22:33:50 +0000 |
|---|---|---|
| committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-05-04 22:33:50 +0000 |
| commit | 8961f7fe604428c163e88e018d2de64b95b13420 (patch) | |
| tree | e1a8f45410e4aae386d1a03103ff841fb8c70b0c | |
| parent | 29117088c98b976a06314e10eff3706f0c6e4579 (diff) | |
| download | flashrom-8961f7fe604428c163e88e018d2de64b95b13420.tar.gz | |
Force enabling SPI mode for SB600 is a bad idea and leads to hangs.
Only access LPC ROM if we boot via LPC ROM. Only access SPI ROM if we
boot via SPI ROM.
The code to force enable SPI is commented out in case someone wants to
reenable it for a particular board with LPC and SPI flash.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | chipset_enable.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 21864af..0395df6 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -680,8 +680,16 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) flashbus = BUS_TYPE_SB600_SPI; /* Enable SPI ROM in SB600 PM register. */ + /* If we enable SPI ROM here, we have to disable it after we leave. + * But how can we know which ROM we are going to handle? So we have + * to trade off. We only access LPC ROM if we boot via LPC ROM. And + * only SPI ROM if we boot via SPI ROM. If you want to do it crossly, + * you have to use the code below. + */ + /* OUTB(0x8f, 0xcd6); OUTB(0x0e, 0xcd7); + */ return 0; } |