diff options
| author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2012-08-26 21:50:36 +0000 |
|---|---|---|
| committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2012-08-26 21:50:36 +0000 |
| commit | d5524a1fae98def385bdca2eaa2aca37ae087fb7 (patch) | |
| tree | 0721bed9cbe360a0a8b1aa19ab461416a659f7f6 | |
| parent | 5c5c6cbb9a1882d6a3cc665e20ee69800e86b4dc (diff) | |
| download | flashrom-d5524a1fae98def385bdca2eaa2aca37ae087fb7.tar.gz | |
Use getpagesize() to determine the physmap's length in nicintel_spi.c.
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | nicintel_spi.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/nicintel_spi.c b/nicintel_spi.c index 531576c..d422b18 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -26,11 +26,13 @@ */ #include <stdlib.h> +#include <unistd.h> #include "flash.h" #include "programmer.h" #include "hwaccess.h" #define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE getpagesize() /* EEPROM/Flash Control & Data Register */ #define EECD 0x10 @@ -157,7 +159,7 @@ static int nicintel_spi_shutdown(void *data) tmp |= FLASH_WRITES_DISABLED; pci_mmio_writel(tmp, nicintel_spibar + EECD); - physunmap(nicintel_spibar, 4096); + physunmap(nicintel_spibar, MEMMAP_SIZE); pci_cleanup(pacc); return 0; @@ -173,7 +175,7 @@ int nicintel_spi_init(void) io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", - io_base_addr, 4096); + io_base_addr, MEMMAP_SIZE); /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, * but other bits with side effects as well. Those other bits must be |