diff options
| author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-10-21 13:20:11 +0000 |
|---|---|---|
| committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-10-21 13:20:11 +0000 |
| commit | a71f516b4b6002ce9b811520397e78abe45422a5 (patch) | |
| tree | a95c81a10ff4ff90dca776cdf5ffed3cf6bab9df /board_enable.c | |
| parent | ebf737e14765afda57da17e965ba39dd1ff19488 (diff) | |
| download | flashrom-a71f516b4b6002ce9b811520397e78abe45422a5.tar.gz | |
Add board enable for ABIT AV8
I disassembled the write enable and the write disable functions from
the Award BIOS image and reconstructed C code to understand for
myself what happens. For details see:
http://www.flashrom.org/pipermail/flashrom/2011-October/008033.html
I compared the download pages of both, abit AV8 and abit AV8-3rd Eye,
and the BIOS downloads are the same. So it's save to assume that this
board enable works on both versions. Tested on AV8.
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'board_enable.c')
| -rw-r--r-- | board_enable.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/board_enable.c b/board_enable.c index 8845844..8dafc83 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1830,6 +1830,22 @@ static int board_mitac_6513wu(void) /* * Suited for: + * - abit AV8: Socket939 + K8T800Pro + VT8237 + */ +static int board_abit_av8(void) +{ + uint8_t val; + + /* Raise GPO pins GP22 & GP23 */ + val = INB(0x404E); + val |= 0xC0; + OUTB(val, 0x404E); + + return 0; +} + +/* + * Suited for: * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F */ @@ -1979,6 +1995,7 @@ const struct board_match board_matches[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, + {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower}, {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise}, |