Fix printing of the Boot BIOS Straps on Intel chipsets

The meaning of the bits involved has changed several times in the past.
This patch takes these changes into account and hence fixes the output of the
pretty printing of GCS on all SPI-supported Intel chipsets that are not ICH7 or
NM10 (the latter were unaffected, because the defaults were correct).

This patch also allows to differentiate Ibex Peak and Cougar Point chipsets from
the earlier chipset series (ICH10) by adding new wrapper functions that set
"ich_generation" to 11 and 12 respectively. This should not change behavior
outside of enable_flash_ich_dc_spi, because the code path for
ich_generation >=9 is equal.

Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
---
defining all those arrays is not very elegant, but i think it is at least very
readable this way. improvements are welcome!
reviewers should have an eye on the codepaths for ich_generation >= 9. i did not
spot a problem, but it should be checked again.

alternatively we could just remove the pretty printing of GCS and just output
the bits involved. i would like to keep the pch differentiation anyway though,
because i feel it will become handy in the future.

tested on my QS57-based thinkpad (probe + partial read)

git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

0 files changed, 0 insertions, 0 deletions