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author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-05-13 22:51:27 +0000 |
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committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-05-13 22:51:27 +0000 |
commit | ab5eae860c2343f51dbb796e066f901b2b4a00d3 (patch) | |
tree | de0f7f28da67b7528a9b35f120fb2ffd410f66ee /dummyflasher.c | |
parent | 57158953195999397301837cc91e282b566341bb (diff) | |
download | flashrom-ab5eae860c2343f51dbb796e066f901b2b4a00d3.tar.gz |
Generic status register prettyprinting for SST25*. Even if we don't tell
the user about the areas the block locking bits correspond to, printing
a detailed list of which lock bits are set is a definite improvement.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Sample output:
[...]
Probing for SST SST25VF032B, 4096 KB: RDID returned bf 25 4a.
probe_spi_rdid_generic: id1 0xbf, id2 0x254a
Chip status register is 1c
Chip status register: Block Protect Write Disable (BPL) is not set
Chip status register: Auto Address Increment Programming (AAI) is not
set
Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
Chip status register: Bit 4 / Block Protect 2 (BP2) is set
Chip status register: Bit 3 / Block Protect 1 (BP1) is set
Chip status register: Bit 2 / Block Protect 0 (BP0) is set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Found chip "SST SST25VF032B" (4096 KB) at physical address 0xffc00000.
Acked-by: Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'dummyflasher.c')
0 files changed, 0 insertions, 0 deletions