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| author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2013-09-14 23:37:01 +0000 |
|---|---|---|
| committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2013-09-14 23:37:01 +0000 |
| commit | 17e6b0728efb89275b94300fa7b72f19e4b68aab (patch) | |
| tree | e322dec9da0fd698ac6bb71c2f0ea2c461df5e5e /flashrom.8.tmpl | |
| parent | fdaef40666cf2dd71e438add8df0ef8a401bec70 (diff) | |
| download | flashrom-17e6b0728efb89275b94300fa7b72f19e4b68aab.tar.gz | |
Enable fwh_idsel parameter for C-ICH and ICH2/3/4/5 chipsets.
Register locations are different from ICH6, but otherwise appear
to have identical bit specifications and defaults.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'flashrom.8.tmpl')
| -rw-r--r-- | flashrom.8.tmpl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 9f8af03..b507a97 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -397,7 +397,7 @@ syntax. If this leads to erase or write accesses to the flash it would most probably bring it into an inconsistent and unbootable state and we will not provide any support in such a case. .sp -If you have an Intel chipset with an ICH6 or later southbridge and if you want +If you have an Intel chipset with an ICH2 or later southbridge and if you want to set specific IDSEL values for a non-default flash chip or an embedded controller (EC), you can use the .sp |