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author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2015-02-10 08:03:10 +0000 |
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committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2015-02-10 08:03:10 +0000 |
commit | 05fae94bad0e0d5522f498a614fbef5f3a27b552 (patch) | |
tree | 340b3f1f7464cfe2a6ef92e2b4e9b7d48b559f41 /hwaccess.c | |
parent | ef82032caba19e59bdd196764345631ae682c983 (diff) | |
download | flashrom-05fae94bad0e0d5522f498a614fbef5f3a27b552.tar.gz |
Add support for SPARC (maybe).
Was implemented by SPARC newbies, does (cross-)compile but is not run-tested.
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'hwaccess.c')
-rw-r--r-- | hwaccess.c | 24 |
1 files changed, 20 insertions, 4 deletions
@@ -49,13 +49,29 @@ int io_fd; */ static inline void sync_primitive(void) { -/* This is needed only on PowerPC because... - * - x86 uses uncached accesses which have a strongly ordered memory model and - * - MIPS uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model - * - ARM uses a strongly ordered memory model for device memories. +/* This is not needed for... + * - x86: uses uncached accesses which have a strongly ordered memory model. + * - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model. + * - ARM: uses a strongly ordered memory model for device memories. + * + * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/memory-barriers.txt */ #if IS_PPC // cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h asm("eieio" : : : "memory"); +#elif IS_SPARC +#if defined(__sparc_v9__) || defined(__sparcv9) + /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like + * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we + * use the strongest hardware memory barriers that exist on Sparc V9. */ + asm volatile ("membar #Sync" ::: "memory"); +#elif defined(__sparc_v8__) || defined(__sparcv8) + /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run + * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable + * operation in the V8 instruction set anyway. If you know better then please tell us. */ + asm volatile ("stbar"); +#else + #error Unknown and/or unsupported SPARC instruction set version detected. +#endif #endif } |