diff options
author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-07-24 15:34:56 +0000 |
---|---|---|
committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-07-24 15:34:56 +0000 |
commit | 45009743941b510e9caa425731e60fcffa1fd3bc (patch) | |
tree | 8606eced9c4d02c7315b9572815b1e022f28f231 /ichspi.c | |
parent | 1ad73d49b174596f86a1e69aa27fb0922ab1e759 (diff) | |
download | flashrom-45009743941b510e9caa425731e60fcffa1fd3bc.tar.gz |
ichspi.c: do not print PBR[3] for ICH7 because it does not exist
intel document 307013 (ICH7 datasheet) section 21.1.9 does only
define PBR[0] (at SPIBAR + 60h) to PBR[2] (SPIBAR + 68h). SPIBAR + 6Ch
and following are not defined, but we were printing them as PBR[3]
anyway. i could not find any references to PBR[3] in documentation of
other related chips (NM10, atom e6xx) either, hence kill it.
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'ichspi.c')
-rw-r--r-- | ichspi.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -1263,7 +1263,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, mmio_readl(ich_spibar + 0x58)); msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c)); - for (i = 0; i < 4; i++) { + for (i = 0; i < 3; i++) { int offs; offs = 0x60 + (i * 4); msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, |