diff options
| author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2014-08-20 15:39:32 +0000 |
|---|---|---|
| committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2014-08-20 15:39:32 +0000 |
| commit | 526905c27f01f5f30a7a60107c028b57bbadef32 (patch) | |
| tree | deaca4de25e5bafc24fe0a48a401a8d4f062a170 /ichspi.c | |
| parent | ea550f88c18554adb2ce21fb7bca18872504ec8b (diff) | |
| download | flashrom-526905c27f01f5f30a7a60107c028b57bbadef32.tar.gz | |
Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton.
The core of this patch to support Bay Trail originally came from the
Chromiumos flashrom repo and was modified by Sage to support the
Rangeley/Avoton parts as well.
Because that was not complicated enough already Stefan Tauner refactored
and refined everything. Bay Trail seems to be the first Atom SoC able to
support hwseq. No SPI Programming Guide could be obtained so it is
handled similarly to Lynx Point which seems to be its nearest relative.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Marc Jones <marcj303@gmail.com>
Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Thomas Reardon <thomas_reardon@hotmail.com>
Tested-by: Wen Wang <wen.wang@adiengineering.com>
Acked-By: Marc Jones <marcj303@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'ichspi.c')
| -rw-r--r-- | ichspi.c | 14 |
1 files changed, 8 insertions, 6 deletions
@@ -612,7 +612,8 @@ static void ich_set_bbar(uint32_t min_addr) bbar_off = 0x50; break; case CHIPSET_ICH8: - msg_perr("BBAR offset is unknown on ICH8!\n"); + case CHIPSET_BAYTRAIL: + msg_pdbg("BBAR offset is unknown!\n"); return; case CHIPSET_ICH9: default: /* Future version might behave the same */ @@ -1739,9 +1740,12 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) msg_pdbg("VSCC: "); prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); } else { - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); + if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + ich_set_bbar(0); + } if (desc_valid) { tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); @@ -1757,10 +1761,8 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); } - ich_set_bbar(0); } - msg_pdbg("\n"); if (desc_valid) { if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); |