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| author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2012-08-17 17:30:43 +0000 |
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| committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2012-08-17 17:30:43 +0000 |
| commit | 0106c62480af1e4f73d2ca91bb3185f28ce7f622 (patch) | |
| tree | 0f623d6207b8dd60a1b1bc939db0a431b7a4d0af /internal.c | |
| parent | 1a53d8e6666c7c2284e697678c832e1a9651c1b9 (diff) | |
| download | flashrom-0106c62480af1e4f73d2ca91bb3185f28ce7f622.tar.gz | |
Bus Pirate init cleanup and fixes.
The Bus Pirate firmware (at least v6.1 and earlier) can't handle UART
input buffer overflow in BBIO mode, and sending a sequence of 0x00 too
fast apparently triggers such an UART input buffer overflow. Wait 10 ms
after sending each 0x00 byte during init to give the Bus Pirate enough
time to handle the input. This fixes a Bus Pirate hang if the previous
flashrom run was aborted by the user.
The Bus Pirate firmware v6.1 and earlier use the wrong (too slow) SPI
speed if more than 2 MHz are requested. Automatically downgrade SPI
speed to 2 MHz for affected firmware versions.
Detect Bus Pirate hardware and firmware versions to allow quirk
handling.
The Bus Pirate init sequence has lots of open-coded sequences which wait
for a given string on the serial line. Refactor them into
buspirate_wait_for_string().
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'internal.c')
0 files changed, 0 insertions, 0 deletions