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author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2013-08-24 12:18:17 +0000 |
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committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2013-08-24 12:18:17 +0000 |
commit | 035011b8d301200c4bf7815ffdfaceaae30e3660 (patch) | |
tree | aac06804cc25ac6df6fcd9c93c37671fede2bbd5 /internal.c | |
parent | cc132eb50ea785800b6efb75540cacb61644b208 (diff) | |
download | flashrom-035011b8d301200c4bf7815ffdfaceaae30e3660.tar.gz |
IT87: Add ability to select between chips on GIGABYTE DualBIOS boards.
Thanks to Vadim Girlin for finding out how to do that.
This is known to work on GA-MA770-UD3, GA-B75M-D3V, GA-B75N and
GA-H61M-S1 (only M_BIOS is populated).
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Tested-by: Damien Zammit <damien@zamaudio.com>
Tested-by: Anton Kochkov <anton.kochkov@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'internal.c')
-rw-r--r-- | internal.c | 5 |
1 files changed, 2 insertions, 3 deletions
@@ -331,9 +331,8 @@ int internal_init(void) return ret; #if defined(__i386__) || defined(__x86_64__) - /* Probe unconditionally for IT87* LPC->SPI translation and for - * IT87* Parallel write enable. - */ + /* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and + * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ init_superio_ite(); #endif |