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| author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-07-27 07:13:06 +0000 |
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| committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-07-27 07:13:06 +0000 |
| commit | 9f952c201f37c3c11ff7542e2befe6832e4acc71 (patch) | |
| tree | ff9f4d8bbe04e1e80755b43b36b990b74d6845b3 /internal.c | |
| parent | 892f2a3364206c172be3a2b9d099da9ed2f41d53 (diff) | |
| download | flashrom-9f952c201f37c3c11ff7542e2befe6832e4acc71.tar.gz | |
Rename CHIP_BUSTYPE_FOO to BUS_FOO.
It's shorter to type, and we have less problems with the 80 column limit.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'internal.c')
| -rw-r--r-- | internal.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -190,7 +190,7 @@ int internal_init(void) /* Default to Parallel/LPC/FWH flash devices. If a known host controller * is found, the init routine sets the buses_supported bitfield. */ - buses_supported = CHIP_BUSTYPE_NONSPI; + buses_supported = BUS_NONSPI; /* Initialize PCI access for flash enables */ pacc = pci_alloc(); /* Get the pci_access structure */ |