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authormkarcher <mkarcher@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>2011-05-11 17:07:07 +0000
committermkarcher <mkarcher@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>2011-05-11 17:07:07 +0000
commit5de0d1e9392bde4665ddb6cd216400e832b8178c (patch)
tree8b556f82073e824bc1e9a4cc9547d67b1d902cee /it85spi.c
parentb23440053e8b3f8fcd0e97f0dbdfb84bed0bbc5f (diff)
downloadflashrom-5de0d1e9392bde4665ddb6cd216400e832b8178c.tar.gz
kill central list of SPI programmers
Remove the array spi_programmer, replace it by dynamic registration instead. Also initially start with no busses supported, and switch to the default non-SPI only for the internal programmer. Also this patch changes the initialization for the buses_supported variable from "everything-except-SPI" to "nothing". All programmers have to set the bus type on their own, and this enables register_spi_programmer to just add the SPI both for on-board SPI interfaces (where the internal programmer already detected the other bus types), as well as for external programmers (where we have the default "none"). Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'it85spi.c')
-rw-r--r--it85spi.c21
1 files changed, 16 insertions, 5 deletions
diff --git a/it85spi.c b/it85spi.c
index a388d10..c6c945b 100644
--- a/it85spi.c
+++ b/it85spi.c
@@ -262,12 +262,22 @@ static int it85xx_spi_common_init(struct superio s)
ce_low = (unsigned char*)(base + 0xD00); /* 0xFFFFFD00 */
#endif
- /* Set this as spi controller. */
- spi_controller = SPI_CONTROLLER_IT85XX;
-
return 0;
}
+static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr, unsigned char *readarr);
+
+static const struct spi_programmer spi_programmer_it85xx = {
+ .type = SPI_CONTROLLER_IT85XX,
+ .max_data_read = 64,
+ .max_data_write = 64,
+ .command = it85xx_spi_send_command,
+ .multicommand = default_spi_send_multicommand,
+ .read = default_spi_read,
+ .write_256 = default_spi_write_256,
+};
+
int it85xx_spi_init(struct superio s)
{
int ret;
@@ -284,7 +294,8 @@ int it85xx_spi_init(struct superio s)
if (buses_supported & CHIP_BUSTYPE_FWH)
msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
/* Really leave FWH enabled? */
- buses_supported |= CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
+ /* Set this as spi controller. */
+ register_spi_programmer(&spi_programmer_it85xx);
}
return ret;
}
@@ -303,7 +314,7 @@ int it85xx_shutdown(void)
* 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get
* data from MISO)
*/
-int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
+static int it85xx_spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
int i;