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author | mkarcher <mkarcher@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-04-15 00:03:37 +0000 |
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committer | mkarcher <mkarcher@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-04-15 00:03:37 +0000 |
commit | 66ec6adea9cd57f6acd031f0c7808b06f14b01be (patch) | |
tree | 6f6ccde262a1878c3e3fe788e4923811a26628ef /it85spi.c | |
parent | 64ecd20bd2874c5b69b2f29225749a7342b71460 (diff) | |
download | flashrom-66ec6adea9cd57f6acd031f0c7808b06f14b01be.tar.gz |
Remove delays in JEDEC erase sequence
It is extremely unlikely that a chip not requiring delays in probe does
require them in erase. We observed unreliable erasing with a SST49LF004A
with these delays, so remove them if the are not required.
In review, I got the hint that "probe_jedec goes further by making that
call conditional on nonzero delay". I decided to ignore that. For
internal_delay, the small amount of clock cycles wasted for calling
programmer_delay(0) is negligible compared to LPC cycle times. It might
be an issue for 5 wasted bytes on the serial line in serprog. OTOH,
flash erase is still slow compared to 6*5 bytes on a serial port at
reasonable speed.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'it85spi.c')
0 files changed, 0 insertions, 0 deletions