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| author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-10-27 22:07:11 +0000 |
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| committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-10-27 22:07:11 +0000 |
| commit | 13db454e0514b749ec93c6a66cff91f3e3a0c909 (patch) | |
| tree | 5b8d6ec01a60208129a46e24a33ab0c18f9012c9 /layout.c | |
| parent | f37c81a74401feed6ab21763af647248abded21e (diff) | |
| download | flashrom-13db454e0514b749ec93c6a66cff91f3e3a0c909.tar.gz | |
Fix internal offset calculations for SPI BYTE PROGRAM and SPI AAI PROGRAM.
The bug was invisible so far because we always started at offset 0. The
pending partial write patch uses nonzero start offsets and trips over
this bug.
Clarify a few comments in IT87 SPI.
Thanks to Idwer Vollering for reporting write breakage with my latest
partial write patch. This should fix the underlying problem.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Idwer Vollering <vidwer@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'layout.c')
0 files changed, 0 insertions, 0 deletions