diff options
author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-05-16 01:23:55 +0000 |
---|---|---|
committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-05-16 01:23:55 +0000 |
commit | 9442edc06e3bdfa80fd8acd948c62122c6a90559 (patch) | |
tree | 7e77126eedcc62dbf83c65cb365d597b7cbb1d03 /nic3com.c | |
parent | 85f5daae23bc62b8796c7e04b5975369c6d68064 (diff) | |
download | flashrom-9442edc06e3bdfa80fd8acd948c62122c6a90559.tar.gz |
Add generic 16 bit and 32 bit chip read/write emulation to the external
flasher infrastructure. The emulation works by splitting 32 bit accesses
into 16 bit accesses and 16 bit accesses into to 8 bit accesses.
That way, external flashers can mix and match the amount of emulation
they need.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'nic3com.c')
-rw-r--r-- | nic3com.c | 18 |
1 files changed, 0 insertions, 18 deletions
@@ -93,14 +93,6 @@ void nic3com_chip_writeb(uint8_t val, volatile void *addr) OUTB(val, io_base_addr + BIOS_ROM_DATA); } -void nic3com_chip_writew(uint16_t val, volatile void *addr) -{ -} - -void nic3com_chip_writel(uint32_t val, volatile void *addr) -{ -} - uint8_t nic3com_chip_readb(const volatile void *addr) { uint8_t val; @@ -110,13 +102,3 @@ uint8_t nic3com_chip_readb(const volatile void *addr) return val; } - -uint16_t nic3com_chip_readw(const volatile void *addr) -{ - return 0xffff; -} - -uint32_t nic3com_chip_readl(const volatile void *addr) -{ - return 0xffffffff; -} |