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authorhailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>2011-07-27 07:13:06 +0000
committerhailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>2011-07-27 07:13:06 +0000
commit9f952c201f37c3c11ff7542e2befe6832e4acc71 (patch)
treeff9f4d8bbe04e1e80755b43b36b990b74d6845b3 /nicintel.c
parent892f2a3364206c172be3a2b9d099da9ed2f41d53 (diff)
downloadflashrom-9f952c201f37c3c11ff7542e2befe6832e4acc71.tar.gz
Rename CHIP_BUSTYPE_FOO to BUS_FOO.
It's shorter to type, and we have less problems with the 80 column limit. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'nicintel.c')
-rw-r--r--nicintel.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/nicintel.c b/nicintel.c
index 2e6e46a..5410523 100644
--- a/nicintel.c
+++ b/nicintel.c
@@ -93,7 +93,7 @@ int nicintel_init(void)
*/
pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
- buses_supported = CHIP_BUSTYPE_PARALLEL;
+ buses_supported = BUS_PARALLEL;
max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;