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authorstefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>2013-09-15 14:17:39 +0000
committerstefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>2013-09-15 14:17:39 +0000
commit0a6d007bbdac28911cd4b22c6c131891df5d1ccb (patch)
treeedbcfbcc9921b732f9c69f2d72e20e184ec2b4b4 /nicintel_spi.c
parent8b90348c7b8a7e50f86687130a9b89a7a16d4c7a (diff)
downloadflashrom-0a6d007bbdac28911cd4b22c6c131891df5d1ccb.tar.gz
sbxxx: Set SPI clock to 16.5 MHz and disable fast reads.
Do not rely on broken firmware to set up the SPI configuration correctly. Some boards fail with flashrom because the firmware chose too high speeds for the alternate SPI mode which flashrom uses. Temporarily change the clock to the lowest common value of 16.5 MHz. Also, disable fast reads just to be safe. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'nicintel_spi.c')
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