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| author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-05-03 21:49:41 +0000 |
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| committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2011-05-03 21:49:41 +0000 |
| commit | 2368caa6fe1973291d4ea3a22e50b03a59e6d917 (patch) | |
| tree | f24b7ce88dfdedbb3388cb3f6e4e44ee4e9f15f0 /nicintel_spi.c | |
| parent | 7287ad057274858806aa3c85dcfb5f2d1d64ccd1 (diff) | |
| download | flashrom-2368caa6fe1973291d4ea3a22e50b03a59e6d917.tar.gz | |
Revert MMIO space writes on shutdown as needed.
Reversible MMIO space writes now use rmmio_write*().
Reversible PCI MMIO space writes now use pci_rmmio_write*().
If a MMIO value needs to be queued for restore without writing it,
use rmmio_val*().
MMIO space writes which are one-shot (e.g. communication with some chip)
should continue to use the permanent mmio_write* variants.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
David tested it successfully on some NM10/ICH7 platforms which switch
between SPI and LPC targets (x86 BIOS ROM vs. EC firmware ROM).
Acked-by: David Hendricks <dhendrix@google.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'nicintel_spi.c')
| -rw-r--r-- | nicintel_spi.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/nicintel_spi.c b/nicintel_spi.c index 3882e81..28d332e 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -148,6 +148,11 @@ int nicintel_spi_init(void) nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); + /* Automatic restore of EECD on shutdown is not possible because EECD + * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, + * but other bits with side effects as well. Those other bits must be + * left untouched. + */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; @@ -167,6 +172,9 @@ int nicintel_spi_shutdown(void) { uint32_t tmp; + /* Disable writes manually. See the comment about EECD in + * nicintel_spi_init() for details. + */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; |