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| author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2014-07-15 13:50:58 +0000 |
|---|---|---|
| committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2014-07-15 13:50:58 +0000 |
| commit | d61c7437f8c0aa69836cab52f4416ffcc10a4047 (patch) | |
| tree | bf2c2e3b17f8673d2857b0d7021fc34d0c124bef /satamv.c | |
| parent | 18e49cb78cc905f2ec540d4271da26735f6d1293 (diff) | |
| download | flashrom-d61c7437f8c0aa69836cab52f4416ffcc10a4047.tar.gz | |
Add support for AMD Bolton chipset.
SPI controller on the bolton chipset uses the same 3-bit speed
settings as Yangtze, but is otherwise the same as the Hudson chips.
Note that the Bolton RRG doesn't specify a speed setting for the bit
setting of 0b111, so I'm assuming that it's the same setting as
Yangtze.
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'satamv.c')
0 files changed, 0 insertions, 0 deletions