diff options
author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-07-27 22:03:46 +0000 |
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committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-07-27 22:03:46 +0000 |
commit | d7a80a4ebe2bf1f1df95ff18cd47c569bf552066 (patch) | |
tree | a384be3a9c9c890870117baf435a0312ecfd4a78 /satasii.c | |
parent | 0a11b8e20c79aa1cbf10c7278b1c7cabe06642b2 (diff) | |
download | flashrom-d7a80a4ebe2bf1f1df95ff18cd47c569bf552066.tar.gz |
Convert all PCI-based external programmers to use special little-endian
accessors for all MMIO regions of PCI devices.
This patch does _not_ touch the internal programmer (which is PCI-based
as well).
Huge thanks go to Misha Manulis who worked with me to create a first
version of this patch for the satasii programmer based on modification
of generic code.
Huge thanks also go to Segher Boessenkool for suggesting the pci_mmio_
prefix for the abstraction layer.
NOTE to package maintainers:
With this patch, compilation and usage of flashrom should be safe on
x86, x86_64, MIPS (little and big endian) and PowerPC (big endian).
The internal programmer is disabled on non-x86/x86_64 (but it compiles).
The atahpt, nic3com, nicnatsemi, nicrealtek and rayer_spi can not be
compiled on non-x86/x86_64 because port space I/O is not (yet)
supported. Please compile with default settings on x86/x86_64 and with
the following settings on all other architectures:
make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_NICNATSEMI=no
CONFIG_RAYER_SPI=no
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Misha Manulis <misha@manulis.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'satasii.c')
-rw-r--r-- | satasii.c | 20 |
1 files changed, 10 insertions, 10 deletions
@@ -61,7 +61,7 @@ int satasii_init(void) sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ - if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) + if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); buses_supported = CHIP_BUSTYPE_PARALLEL; @@ -80,32 +80,32 @@ void satasii_chip_writeb(uint8_t val, chipaddr addr) { uint32_t ctrl_reg, data_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set writes and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff); - data_reg = (mmio_readl((sii_bar + 4)) & ~0xff) | val; - mmio_writel(data_reg, (sii_bar + 4)); - mmio_writel(ctrl_reg, sii_bar); + data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val; + pci_mmio_writel(data_reg, (sii_bar + 4)); + pci_mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ; } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; - while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; + while ((ctrl_reg = pci_mmio_readl(sii_bar)) & (1 << 25)) ; /* Mask out unused/reserved bits, set reads and start transaction. */ ctrl_reg &= 0xfcf80000; ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff); - mmio_writel(ctrl_reg, sii_bar); + pci_mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (pci_mmio_readl(sii_bar) & (1 << 25)) ; - return (mmio_readl(sii_bar + 4)) & 0xff; + return (pci_mmio_readl(sii_bar + 4)) & 0xff; } |