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| author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-07-14 16:19:05 +0000 |
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| committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-07-14 16:19:05 +0000 |
| commit | 395dd1d1e2d37d90416e6d296a5f1f79bb320842 (patch) | |
| tree | a9049f708d0ab7d42d122fecd23855aaa819c5bc /sb600spi.c | |
| parent | e8db2112db803b2c94a9fb55b136ebebda08c1ce (diff) | |
| download | flashrom-395dd1d1e2d37d90416e6d296a5f1f79bb320842.tar.gz | |
Convert SPI chips to partial write, but wrap the write functions in a
compat layer to allow converting the rest of flashrom later.
I actually have patches for most of the remaining conversion, but I
wanted to get this out and reviewed first.
Tested on Intel NM10 by David Hendricks.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'sb600spi.c')
| -rw-r--r-- | sb600spi.c | 19 |
1 files changed, 2 insertions, 17 deletions
@@ -48,25 +48,10 @@ int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) return spi_read_chunked(flash, buf, start, len, 8); } -/* FIXME: SB600 can write 5 bytes per transaction. */ -int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) +int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { - int total_size = flash->total_size * 1024; - int result = 0; - spi_disable_blockprotect(); - /* Erase first */ - msg_pinfo("Erasing flash before programming... "); - if (erase_flash(flash)) { - msg_perr("ERASE FAILED!\n"); - return -1; - } - msg_pinfo("done.\n"); - - msg_pinfo("Programming flash"); - result = spi_write_chunked(flash, buf, 0, total_size, 5); - msg_pinfo(" done.\n"); - return result; + return spi_write_chunked(flash, buf, start, len, 5); } static void reset_internal_fifo_pointer(void) |