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| author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2013-06-16 10:30:08 +0000 |
|---|---|---|
| committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2013-06-16 10:30:08 +0000 |
| commit | 46dd0ea6e7e4f7ce82fdef7d34bc94046820415b (patch) | |
| tree | ef4b7b69bdbe80c9a3177341811dce516e7bbd74 /sb600spi.c | |
| parent | 41dd803b9ea5e65bacc418c67a7a476b12e88508 (diff) | |
| download | flashrom-46dd0ea6e7e4f7ce82fdef7d34bc94046820415b.tar.gz | |
sbxxx: spibar[0] debug print refinements.
Newer models support a 66 MHz clock and fast reads.
We should probably distinguish the models better (as we do in ichspi)
and add support for frequency selection etc. For now this has to
suffice.
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'sb600spi.c')
| -rw-r--r-- | sb600spi.c | 5 |
1 files changed, 3 insertions, 2 deletions
@@ -211,7 +211,7 @@ int sb600_probe_spi(struct pci_dev *dev) uint32_t tmp; uint8_t reg; static const char *const speed_names[4] = { - "Reserved", "33", "22", "16.5" + "66/reserved", "33", "22", "16.5" }; /* Read SPI_BaseAddr */ @@ -250,9 +250,10 @@ int sb600_probe_spi(struct pci_dev *dev) * SB700 or later, reads and writes will be corrupted. Abort in this * case. Make sure to avoid this check on SB600. */ - msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + msg_pdbg("(0x%08" PRIx32 ") fastReadEnable=%u, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", + tmp, (tmp >> 18) & 0x1, (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); |