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| author | mkarcher <mkarcher@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-07-22 18:04:15 +0000 |
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| committer | mkarcher <mkarcher@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2010-07-22 18:04:15 +0000 |
| commit | 6b6a8d1ec5b9726c579767b62f41f14ae0fb6cf0 (patch) | |
| tree | 9a784e968db73ec1e95bd27efe7aa3d7c7ca9a8e /sb600spi.c | |
| parent | 0adc9d29a81c15e7acef494f2d78ad55f3206d43 (diff) | |
| download | flashrom-6b6a8d1ec5b9726c579767b62f41f14ae0fb6cf0.tar.gz | |
Move Intel SPI initialisation to ichspi.c
Smarter version could decide whether SPI is vital or not depending on
straps. Straps are currently implemented for ICH7. EP80579 is in the comment,
PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI".
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'sb600spi.c')
0 files changed, 0 insertions, 0 deletions