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| author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-12-17 15:20:01 +0000 |
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| committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-12-17 15:20:01 +0000 |
| commit | 9e04311e5b57ad40acc3828fae239556bfcc41d0 (patch) | |
| tree | 017b795c2d6162201b952ae400edabfd3be04fba /sb600spi.c | |
| parent | 79128a97257fcf4c2d03daac2c704ddec36c9f87 (diff) | |
| download | flashrom-9e04311e5b57ad40acc3828fae239556bfcc41d0.tar.gz | |
Use the maximum decode size infrastructure.
- Detect max FWH size for Intel
631xESB/632xESB/3100/ICH6/ICH7/ICH8/ICH9/ICH10.
- Move IDSEL override before decode size checking for the chipsets
listed above or flashrom will complain based on old values.
- Adjust supported flash buses for the chipsets listed above (none of
them supports LPC or Parallel).
- Detect max parallel size for AMD/National Semiconductor CS5530.
- Adjust supported flash buses for CS5530/CS5530A.
- Set board-specific max decode size for Elitegroup K7VTA3.
- Set board-specific max decode size for Shuttle AK38N.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'sb600spi.c')
0 files changed, 0 insertions, 0 deletions