serprog: Fix FWH/LPC by implementing serprog_map.

The serprog protocol does only transmit 24 bit-wide address and ignores the
top 8 bit. This is fine as long as the underlying hardware ignores the latter
anyway (which is the case for parallel chips that even lack the respective pins).
FWH/LPC chips, however, operate on a full 32-bit (LPC) or 28-bit (FWH) address
space and would fail with the fallback mapping to NULL.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>

git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 16 insertions, 0 deletions

diff --git a/serprog.c b/serprog.c
index 3de0182..a2a3fe0 100644
--- a/serprog.c
+++ b/serprog.c
@@ -943,3 +943,19 @@ static int serprog_spi_read(struct flashctx *flash, uint8_t *buf,
 	}
 	return 0;
 }
+
+void *serprog_map(const char *descr, uintptr_t phys_addr, size_t len)
+{
+	/* Serprog transmits 24 bits only and assumes the underlying implementation handles any remaining bits
+	 * correctly (usually setting them to one either in software (for FWH/LPC) or relying on the fact that
+	 * the hardware observes a subset of the address bits only). Combined with the standard mapping of
+	 * flashrom this creates a 16 MB-wide window just below the 4 GB boundary where serprog can operate (as
+	 * needed for non-SPI chips). Below we make sure that the requested range is within this window. */
+	if ((phys_addr & 0xFF000000) == 0xFF000000) {
+		return (void*)phys_addr;
+	} else {
+		msg_pwarn(MSGHEADER "requested mapping %s is incompatible: 0x%zx bytes at 0x%0*" PRIxPTR ".\n",
+			  descr, len, PRIxPTR_WIDTH, phys_addr);
+		return NULL;
+	}
+}