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authorstefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>2013-06-28 21:28:43 +0000
committerstefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>2013-06-28 21:28:43 +0000
commit98b3c95ee0364399b858f9c177102fcea751be93 (patch)
treeb5193c315ee7ea51071874ed8c30435a4aee7e71 /spi25_statusreg.c
parent9552530bfd78429c2e1c8b64f150196c10ad1996 (diff)
downloadflashrom-98b3c95ee0364399b858f9c177102fcea751be93.tar.gz
Add support for Nantronics N25 series.
Add... - N25S10 - N25S20 - N25S40 - N25S80 - N25S16 Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'spi25_statusreg.c')
-rw-r--r--spi25_statusreg.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index e0ed690..5560f5b 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -223,10 +223,10 @@ static void spi_prettyprint_status_register_hex(uint8_t status)
msg_cdbg("Chip status register is 0x%02x.\n", status);
}
-/* Common highest bit: Status Register Write Disable (SRWD). */
+/* Common highest bit: Status Register Write Disable (SRWD) or Status Register Protect (SRP). */
static void spi_prettyprint_status_register_srwd(uint8_t status)
{
- msg_cdbg("Chip status register: Status Register Write Disable (SRWD) is %sset\n",
+ msg_cdbg("Chip status register: Status Register Write Disable (SRWD, SRP, ...) is %sset\n",
(status & (1 << 7)) ? "" : "not ");
}