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| author | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2012-12-29 15:04:12 +0000 |
|---|---|---|
| committer | stefanct <stefanct@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2012-12-29 15:04:12 +0000 |
| commit | baf53a1e3972310eab38b0062a192f2e4c076227 (patch) | |
| tree | b394950b3bd52b2490e1da77a1c497516d6bfd06 /spi25_statusreg.c | |
| parent | a89c7d9422f46ea1d9e6bd6b660c52b5015fdb2a (diff) | |
| download | flashrom-baf53a1e3972310eab38b0062a192f2e4c076227.tar.gz | |
Add support for Intel S33 series flash chips.
This includes:
Bottom boot block:
* 16Mb/2MB:
QB25F160S33B8, QB25F016S33B8, QH25F160S33B8, QH25F016S33B8
* 32Mb/4MB:
QB25F320S33B8, QH25F320S33B8
* 64Mb/8MB:
QB25F640S33B8, QH25F640S33B8
Top boot block:
* 16Mb/2MB:
QB25F160S33T8, QB25F016S33T8, QH25F160S33T8, QH25F016S33T8
* 32Mb/4MB:
QB25F320S33T8, QH25F320S33T8
* 64Mb/8MB:
QB25F640S33T8, QH25F640S33T8
At least some seem to be marketed by other vendors (too?) but also with
Intel's vendor ID.
Besides a 0xC7 chip erase and a 0xD8 uniform 64kB block erase they
support also erasing the top/bottom 8 8kB blocks with opcode 0x40.
But since this command fails for all addresses outside those ranges,
it is not easily implemented with flashrom's current code base and
hence left out.
Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'spi25_statusreg.c')
| -rw-r--r-- | spi25_statusreg.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 84e8f63..2e01c06 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -468,6 +468,29 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0); } +/* === Intel === */ + +/* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */ +int spi_disable_blockprotect_s33(struct flashctx *flash) +{ + return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0); +} + +int spi_prettyprint_status_register_s33(struct flashctx *flash) +{ + uint8_t status = spi_read_status_register(flash); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_srwd(status); + msg_cdbg("Chip status register: Program Fail Flag (P_FAIL) is %sset\n", + (status & (1 << 6)) ? "" : "not "); + msg_cdbg("Chip status register: Erase Fail Flag (E_FAIL) is %sset\n", + (status & (1 << 5)) ? "" : "not "); + spi_prettyprint_status_register_bp(status, 2); + spi_prettyprint_status_register_welwip(status); + return 0; +} + /* === SST === */ static void spi_prettyprint_status_register_sst25_common(uint8_t status) |