Add SPI multicommand infrastructure.

Some SPI opcodes need to be sent in direct succession after each other
without any chip deselect happening in between. A prominent example is
WREN (Write Enable) directly before PP (Page Program). Intel calls the
first opcode in such a row "preopcode".

Right now, we ignore the direct succession requirement completely and it
works pretty well because most onboard SPI masters have a timing or
heuristics which make the problem disappear.
The FT2232 SPI flasher is different. Since it is an external flasher,
timing is very different to what we can expect from onboard flashers and
this leads to failure at slow speeds.

This patch allows any function to submit multiple SPI commands in a
stream to any flasher. Support in the individual flashers isn't
implemented yet, so there is one generic function which passes the each
command in the stream one-by-one to the command functions of the
selected SPI flash driver.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
Tested-by: Jakob Bornecrantz <wallbraker@gmail.com>


git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 1 insertions, 1 deletions

diff --git a/wbsio_spi.c b/wbsio_spi.c
index 9ac15d1..cbdddd2 100644
--- a/wbsio_spi.c
+++ b/wbsio_spi.c
@@ -90,7 +90,7 @@ int wbsio_check_for_spi(const char *name)
  * Would one more byte of RAM in the chip (to get all 24 bits) really make
  * such a big difference?
  */
-int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt,
+int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt,
 		      const unsigned char *writearr, unsigned char *readarr)
 {
 	int i;