diff options
| author | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-05-09 02:09:45 +0000 |
|---|---|---|
| committer | hailfinger <hailfinger@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1> | 2009-05-09 02:09:45 +0000 |
| commit | 73cf3df4999eddd433c1d8dfd1da500afab96721 (patch) | |
| tree | 9bd6460e4a69d0647706ab139184870b32244441 /wbsio_spi.c | |
| parent | ab8d21b08b8b58d8a136a75b912f1d677287efe2 (diff) | |
| download | flashrom-73cf3df4999eddd433c1d8dfd1da500afab96721.tar.gz | |
Until the ICH SPI driver can handle preopcodes as standalone opcodes, we
should handle such special opcode failure gracefully on ICH and
compatible chipsets.
This fixes chip erase on almost all ICH+VIA SPI masters.
Thanks to Ali Nadalizadeh for helping track down this bug!
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'wbsio_spi.c')
| -rw-r--r-- | wbsio_spi.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/wbsio_spi.c b/wbsio_spi.c index a3e96fd..6ab277a 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -189,6 +189,7 @@ int wbsio_spi_read(struct flashchip *flash, uint8_t *buf) int wbsio_spi_write(struct flashchip *flash, uint8_t *buf) { int pos, size = flash->total_size * 1024; + int result; if (flash->total_size > 1024) { fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__); @@ -196,7 +197,9 @@ int wbsio_spi_write(struct flashchip *flash, uint8_t *buf) } flash->erase(flash); - spi_write_enable(); + result = spi_write_enable(); + if (result) + return result; for (pos = 0; pos < size; pos++) { spi_byte_program(pos, buf[pos]); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) |