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* Chips like the SST SST25VF080B can only handle single byte writeshailfinger2009-05-096-16/+50
| | | | | | | | | | | | | | | | | | | outside AAI mode. Change SPI architecture to handle 1-byte chunk chip writing differently from 256-byte chunk chip writing. Annotate SPI chip write functions with _256 or _1 suffix denoting the number of bytes they write at maximum. The 1-byte chunk writing is cut-n-pasted to different SPI drivers right now. A later patch can move them to the generic spi_chip_write_1. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Until the ICH SPI driver can handle preopcodes as standalone opcodes, wehailfinger2009-05-094-16/+54
| | | | | | | | | | | | | | | should handle such special opcode failure gracefully on ICH and compatible chipsets. This fixes chip erase on almost all ICH+VIA SPI masters. Thanks to Ali Nadalizadeh for helping track down this bug! Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a dummy external flasher which just prints each operation.hailfinger2009-05-095-2/+104
| | | | | | | | | | | | | Usage: flashrom --programmer dummy This is a great way to test flashrom without root access. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split vendor name and board name into two fields as preparationuwe2009-05-091-42/+47
| | | | | | | | | | | for wiki output of supported stuff. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add --programmer to help text and man page.hailfinger2009-05-092-0/+6
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make chipset list alphabetically ordered as the other lists.uwe2009-05-081-39/+40
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add external flasher support:hailfinger2009-05-084-91/+233
| | | | | | | | | | | | | | | | | | - Read/write accesses through function pointers - Command line parameter for internal/external flasher - Board and chipset setup moved to internal init function - Shutdown stuff moved to internal shutdown function As a side benefit, this will allow us to undo chipset write enable during shutdown. Tested by Uwe on real hardware. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Re-add a line which got deleted in r473 by accident.hailfinger2009-05-081-0/+2
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Keep list of boards alphabetically sorted. This is (among other things)uwe2009-05-081-20/+21
| | | | | | | | | | | | useful/required for the -L output and the upcoming wiki-syntax output of supported boards. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Flashrom assumes that the flash chip contents are available via mmap ifhailfinger2009-05-083-13/+134
| | | | | | | | | | | | | | | no read function is defined. This special case is handled in lots of places all over the code. Remove the special case and use the read_memmapped function. Not only does this allow us to fix a read bug in flashrom I recently uncovered on ICH SPI, it also allows us to add support for Paraflasher to flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Store and display chipset test status (not only chip status).uwe2009-05-071-83/+91
| | | | | | | | | | | | | | The list of tested chipsets is synced from the wiki. Also, split the chipset vendor and name into two fields for easier wiki-syntax output later. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Always print the flashrom version as first output line.hailfinger2009-05-071-1/+3
| | | | | | | | | | Suggested by Peter Stuge. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ASD chips may exist, but all available docs suggest they are justhailfinger2009-05-061-0/+1
| | | | | | | | | | | | rebranded Winbond chips with Winbond IDs. The ASD vendor/chip IDs in flash.h are very likely just misinterpreted LHA headers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Clarify error message in enable_flash_sb600() a little.stuge2009-05-061-1/+1
| | | | | | | | Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Improve SST25 status register routines:hailfinger2009-05-061-11/+15
| | | | | | | | | | | | | - Using a 4-bit index into an array with 8 elements leads to out-of-bounds accesses. Use proper bit masking to fix this. - Factor out common SST25 status register printing. - Use the common SST25 status register printing for SST25VF080B. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Revert r466 because it introduced a bug:hailfinger2009-05-061-5/+6
| | | | | | | | | | If unprotect succeeded, it will print "SB600 unprotect failed". Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Cleanup redundant condition and clarify message a little.stuge2009-05-061-6/+5
| | | | | | | | Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Touch up some error messages in enable_flash_cs5536().stuge2009-05-061-2/+2
| | | | | | | | Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Clean up the SB400 chipset enable code. Use pci_dev_find() instead ofhailfinger2009-05-061-9/+1
| | | | | | | | | | setting up a filter and iterating over PCI devices. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rewrite the SB600 chipset enable function:hailfinger2009-05-051-17/+33
| | | | | | | | | | | | | | | | | - Check for read/write protected regions first. - Region protection is write-once according to the data sheets. Check if the write succeeded. Don't write if the region is not protected. - Verbose region protection dumping. - Improve readability of BAR mapping code. - Align BAR mapping to a page boundary (4k) instead of a 16k boundary. This patch prepares the code for a SPI detection heuristic. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Here is a fix for chipset_enable.c when there is not /dev/cpu. Openmyles2009-05-051-1/+1
| | | | | | | | | | fails so there is no reason to lseek in. Actually this is a trivial fix for a bad return value from open. Signed-off-by: Bertrand Jacquin <beber@meleeweb.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* SST25VF080B TEST_OK_ ERASE WRITEstuge2009-05-051-1/+1
| | | | | | | | | | As reported by A. Spamlover. Thanks! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Some cosmetics in README and manpage. Also, move more stuff to the manpageuwe2009-05-052-57/+68
| | | | | | | | | | | where it belongs (this also eliminates some duplicated contents). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Force enabling SPI mode for SB600 is a bad idea and leads to hangs.hailfinger2009-05-041-0/+8
| | | | | | | | | | | | | Only access LPC ROM if we boot via LPC ROM. Only access SPI ROM if we boot via SPI ROM. The code to force enable SPI is commented out in case someone wants to reenable it for a particular board with LPC and SPI flash. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* SST25VF080B TEST_OK_READstuge2009-05-041-1/+1
| | | | | | | | | | Per report from from Henning Fleddermann. Thanks! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Onwards with development. Re-add the svn revision to the version string.hailfinger2009-05-041-2/+4
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* flashrom 0.9.0hailfinger2009-05-042-5/+3
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Complement the README file with build instructions for the platforms itstuge2009-05-031-1/+10
| | | | | | | | | | currently compiles on. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix compilation on Solaris and tell people how to compile flashrom onhailfinger2009-05-013-7/+29
| | | | | | | | | | | | Solaris, Darwin/Mac OS X and DragonFly BSD. Thanks to Joerg Schilling and Patrick Georgi for the Solaris part. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Mention that flashrom can also verify flash contents.stuge2009-05-012-4/+4
| | | | | | | | Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix usage to show that vendor: is optional in the -m parameter.stuge2009-05-011-1/+1
| | | | | | | | Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Some functions take no arguments. Make that explicit in the associatedhailfinger2009-05-011-5/+5
| | | | | | | | | | | prototypes. This avoids a warning on some compilers and is a correctness issue. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Li-Ta (Ollie) Lo to the author list.hailfinger2009-05-011-0/+2
| | | | | | | | | | | | He started flashrom back in 2000. Thanks to Ron for pointing this out. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Since the command line interface for flashrom will change for 1.0hailfinger2009-05-012-0/+9
| | | | | | | | | | | (all-caps or no-caps for short options, exclude range syntax, etc.) we should tell users in the man page and the usage message about this. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* flashrom: Macronix MX25L1605 TEST_OK_ PROBE READ ERASE WRITEstuge2009-04-291-1/+1
| | | | | | | | | | Per report from Aldrik Dunbar. Thanks! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* There are still some tweaks necessary to get Flashrom to build onhailfinger2009-04-282-3/+3
| | | | | | | | | | | DragonFly, but this helps a lot. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Enable scan-build for flashrom.oxygene2009-04-261-2/+2
| | | | | | | | Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4211hailfinger2009-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | The flashrom makefile wants to redirect both stdout and stderr to /dev/null for one compile test. The old variant of using &>/dev/null works on bash and zsh, but not on dash and tcsh. dash and tcsh interpret it as "background command and truncate /dev/null" which is not what we want. >& works on tcsh and bash, but it is not POSIX compliant. Since make uses /bin/sh and /bin/sh has to be POSIX compliant, we can use the POSIX variant of stderr and stdout redirection. >/dev/null 2>&1 is POSIX compliant. This is specified in SuSv3, Shell Command Language, sections 2.7.2 and 2.7.6. Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4205uwe2009-04-242-5/+5
| | | | | | | | | | | MAX may already be defined. Also, fix smaller cosmetics (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4200stuge2009-04-232-1/+15
| | | | | | | | | | flashrom: Support MX25L3235D Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4196uwe2009-04-232-26/+5
| | | | | | | | | | | | Don't duplicate option description in README, the manpage already has that info. Also, additional small cosmetic fix. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4177hailfinger2009-04-221-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | All "unknown xy SPI chip" entries claim to have status UNTESTED for probe/read/erase/write. That is incorrect. A bit of confusion comes from how the #defines are named. We call them TEST_BAD_*, but the message printed by flashrom says: "This flash part has status NOT WORKING for operations:" Something that is unimplemented is definitely not working. Neither of the chip entries mentioned above has erase or write functions implemented, so erase and write are not working. Since their size is unknown, we can't read them in. That means read is not working as well. Probing is a different matter. If a chip-specific probe function had matched, we wouldn't have to handle the chip with the "unknown xy SPI chip" fallback. I'm tempted to call that "not working" as well, but I'm open to discussion on this point. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4161hailfinger2009-04-211-0/+2
| | | | | | | | | | | | | flashrom: Add support for Gigabyte GA-MA790FX-DQ6. This board uses IT8718F LPC->SPI translation for the flash chip. Tested by Mateusz Murawski. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Mateusz Murawski <matowy@tlen.pl> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4150stuge2009-04-212-0/+15
| | | | | | | | | | flashrom: Support Macronix MX2512805D flash chip Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4149stuge2009-04-211-1/+1
| | | | | | | | | | flashrom: Trivial indent fix Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4146hailfinger2009-04-201-7/+8
| | | | | | | | | | | After verification in datasheets, all MX25 accept the same opcodes 0x60 and 0xC7 for Chip Erase. Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4142stuge2009-04-201-421/+43
| | | | | | | | | | | | | | | | flashrom: board_enables: reconstruct table. This patch restores the pciid based board matching table. It makes this table readable and hackable again, and the only disadvantage is that the right margin is way beyond the rather dogmatic 80. All 0x0000 pci ids have been string replaced by 0 to more easily spot missing ids, and extra comments have been added to explain how the various entries are used. Signed-Off-By: Luc Verhaegen <libv@skynet.be> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4141stuge2009-04-201-5/+5
| | | | | | | | | | flashrom: Trivial README change Flashrom->flashrom Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4139stuge2009-04-191-2/+2
| | | | | | | | | | flashrom: MX25L1605 and 1635 accept Chip Erase opcodes 60 and C7 Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4138hailfinger2009-04-191-0/+13
| | | | | | | | | | Add MX25L1635D support, as discussed on #coreboot. Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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