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* Add support for FT232H.stefanct2012-09-261-0/+12
| | | | | | | | | | | | For older versions of libftdi we define TYPE_232H ourselves and this seems to be enough to get at least basic support (and we don't need more than that AFAICT). Signed-off-by: Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce a compile time option to select a default programmer.stefanct2012-09-251-0/+14
| | | | | | | | | | Heavily influenced by a discussion with (and based on code from) Peter Stuge. Please read the comment in the Makefile before using this option. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Allow specifying CPPFLAGShailfinger2012-08-151-3/+3
| | | | | | | | | | | | | The user may know better which CFLAGS/CPPFLAGS are appropriate. Use FLASHROM_CFLAGS for flags which flashrom definitely needs to build. Thanks to Stefan Tauner for pointing out the flaw in r1574. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Allow the user to specify CFLAGS without breaking the buildhailfinger2012-08-141-2/+5
| | | | | | | | | | | | | | | | | | | | GNU make has a very interesting quirk: If you set a variable on the command line, any changes to that variable in the Makefile are ignored unless marked with the "override" keyword. Use CFLAGS only for optimization and warning options, and use CPPFLAGS for the dependency and other preprocessor related options. That way packagers can specify their own CFLAGS without breaking the build. As a side benefit, the ich_descriptors_tool Makefile now behaves exactly the same whether called standalone or as part of the main Makefile. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Portability fixes and cleanupshailfinger2012-08-091-17/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move Mac OS X IOKit/DirectHW availability checks in the Makefile from compiler check to pciutils check. Print the compiler error messages for feature detection. Add DOS libpci in the Makefile includes only if a PCI-based programmer was requested. Restrict mmap usage in ich_descriptors_tool to Unix style systems. Build ich_descriptors_tool with the correct .exe extension on DOS/Windows. Build ich_descriptors_tool by default on x86. (Patch by Stefan Tauner) Print the Windows version instead of "unknown machine" on Windows. Don't #define our own __DARWIN__, use the standard OS X detection method. Update the README. Add more generated files to svn:ignore Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.6.1hailfinger2012-08-081-1/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.6hailfinger2012-08-021-1/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 13.stefanct2012-07-281-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested Mainboards: OK: - ASRock A780FullHD http://www.flashrom.org/pipermail/flashrom/2012-July/009599.html - ASRock 880G Pro3 http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html - ASRock N61P-S http://www.flashrom.org/pipermail/flashrom/2012-May/009316.html - ASUS M2N68-VM http://www.flashrom.org/pipermail/flashrom/2012-May/009334.html - ASUS M3N78 PRO http://www.flashrom.org/pipermail/flashrom/2012-July/009519.html - ASUS M4N68T V2 http://www.flashrom.org/pipermail/flashrom/2012-May/009277.html - ASUS M5A78L-M LX reported by clavile on IRC - ASUS P8P67 PRO (rev. 3.0) http://www.flashrom.org/pipermail/flashrom/2012-April/009188.html - ASUS P8Z68-V reported by Kano on IRC http://paste.flashrom.org/view.php?id=1232 - ASUS SABERTOOTH 990FX http://paste.flashrom.org/view.php?id=1214 - Dell Inspiron 1420 http://www.flashrom.org/pipermail/flashrom/2012-May/009196.html - ECS GF8200A http://www.flashrom.org/pipermail/flashrom/2012-May/009256.html - GIGABYTE GA-H61M-D2H-USB3 http://www.flashrom.org/pipermail/flashrom/2012-May/009333.html - MSI MS-7250 (K9N SLI (rev 2.1)) http://www.flashrom.org/pipermail/flashrom/2012-June/009436.html - MSI MS-7676 (Z68MA-G45 (B3)) http://www.flashrom.org/pipermail/flashrom/2012-June/009424.html - Palit N61S http://www.flashrom.org/pipermail/flashrom/2012-May/009212.html NOT OK: - ASRock H61M-ITX http://www.flashrom.org/pipermail/flashrom/2012-May/009224.html - Dell Latitude E6520 http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html - Dell Vostro 3700 http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html - Intel DH61AG http://www.flashrom.org/pipermail/flashrom/2012-June/009417.html - Intel DQ965GF http://www.flashrom.org/pipermail/flashrom/2012-May/009295.html - HP/Compaq 8100 Elite CMT PC (304Bh) http://paste.flashrom.org/view.php?id=1182 - HP Z400 Workstation (0AE4h) http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html - Supermicro X9DR3-F http://www.flashrom.org/pipermail/flashrom/2012-June/009422.html Tested flash chips: - mark AMIC A25L032 as TEST_OK_PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-June/009363.html - mark Atmel AT25DF321A as TEST_OK_PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html - mark Atmel AT26DF161 as TEST_OK_PR (+PR) http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html - mark Eon EN25QH16 as TEST_OK_PR (+PR) http://www.flashrom.org/pipermail/flashrom/2012-July/009566.html - mark SST SST39VF010 as TEST_OK_PREW (+W) http://www.flashrom.org/pipermail/flashrom/2012-June/009425.html - mark ST M25P64 as TEST_OK_PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html Tested chipset enables: - Intel 3420 http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html - Add board enable for ASUS P5GD2-X lspci: http://paste.flashrom.org/view.php?id=1234 write: http://paste.flashrom.org/view.php?id=1240 Miscellaneous - Reorder some boards in print.c. - Remove broken abit URLs. - Whitespace changes. - Fix the maximum number of southbridge straps in the ICH descriptor structs. - Refine documentation regarding ICH region lock bits. - Demote verbosity of ICH Opcode reprogramming to -VV. - Exclude Pony-SPI for DOS targets (missing serial support). Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove sharplhf00l04.c.stefanct2012-05-161-1/+1
| | | | | | | | | | | The currently unreferenced function in sharplhf00l04.c does a standard FWH block protection reset (writes 0 to the protection register) and a standard FWH block erase. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add serial port bitbanging codemkarcher2012-04-301-0/+13
| | | | | | | | | | | This adds the pony_spi driver which supports the SI_Prog adapter, which is commonly used for SPI chips with PonyProg 2000, and a custom adapter called "SERBANG" which differs in the logic of two pins. Signed-off-by: Virgil-Adrian Teaca <darkstarlinux@gmail.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Eon EN29LV640B chip.uwe2012-04-141-1/+1
| | | | | | | | | | | | | | This chip needs special command sequences in 8 bit mode. Also, 8 bit programming needs actually 16bit double byte program. The chip is found on the Bifferos Bifferboard, for example. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make the presence of Linux SPI headers mandatory for linux_spi.stefanct2012-03-131-1/+22
| | | | | | | | | | | This solution is copied from ft2232_spi and is equally hacky. Thanks to M.K. for investigating the history of <linux/spi/spidev.h>, which led to a hopefully more robust check. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.5.2hailfinger2012-03-081-1/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.5.1hailfinger2012-02-251-1/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.5hailfinger2012-02-181-1/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for SFDP (JESD216).stefanct2012-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to modules using the opaque programmer framework (e.g. ICH Hardware Sequencing) this uses a template struct flashchip element in flashchips.c with a special probe function that fills the obtained values into that struct. This allows yet unknown SPI chips to be supported (read, erase, write) almost as if it was already added to flashchips.c. Documentation used: http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) W25Q32BV data sheet Revision F (2011-04-01) EN25QH16 data sheet Revision F (2011-06-01) MX25L6436E data sheet Revision 1.8 (2011-12-26) Tested-by: David Hendricks <dhendrix@google.com> on W25Q64CV + dediprog Tested-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> on a 2010 MX25L6436E with preliminary (i.e. incorrect) SFDP implementation + serprog Thanks also to Michael Karcher for his comments and preliminary review! Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Document and enable the linux_spi driverhailfinger2012-02-161-9/+16
| | | | | | | | | | | The linux_spi driver is now enabled by default on Linux. A man page entry and a line in --list-supported output have been added. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support compilation for the ARM architecture (little-endian only).hailfinger2012-02-131-2/+3
| | | | | | | | | | | | | | Note: The internal programmer will abort during processor check. This is intentional. The other hardware drivers (except those using port I/O) should work. Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: David Hendricks <dhendrix@google.com> Tested-by: Timo Juhani Lindfors <timo.lindfors@iki.fi> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Cross-compilation fixeshailfinger2011-12-201-25/+42
| | | | | | | | | | | | | | | | | | | | | | | Switch from host OS detection to target OS detection. Complain about unknown target OS/architecture. Disable annoying format string warnings on DJGPP. Native and cross-compilation now usually just require setting CC. Examples: make CC=i586-pc-msdosdjgpp-gcc make CC="clang -m64" make CC=i686-w64-mingw32-gcc Tested for a boatload of native and cross compilation configurations. There is a new target "make libpayload" in case you don't want to specify all tools by hand. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add opaque programmer registration infrastructurehailfinger2011-11-041-1/+1
| | | | | | | | | | | | | An opaque programmer does not allow direct flash access and only offers abstract probe/read/erase/write methods. Due to that, opaque programmers need their own infrastructure and registration framework. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDODstefanct2011-09-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for correct layout before taking any action on runtime. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Linux SPI subsystem (spidev).uwe2011-09-031-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | See http://www.kernel.org/doc/Documentation/spi/spidev for an introduction. Usage is as follows: flashrom -p linux_spi:dev=/dev/spidevX.Y where X is the bus number, and Y device. It accepts an optional parameter 'speed' which allows to set the SPI clock speed in kHz. Tested on an Atmel AVR32AP7000 board (NGW100 Network Gateway Kit), see below, which was used to program a ThinkPad X60, but it should work on every other Linux system, too. http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4102) Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Makefile: Fix MinGW build, improve output with bogus CC.uwe2011-08-201-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | As per IRC discussion, the "ARCH :=" line should be moved after any lines which set CC, as it uses CC itself. This fixes the MinGW build. Also, add a "2>/dev/null" in the "ARCH :=" as per suggestion from Stefan Tauner to improve the output in the case CC is bogus: Before: $ make CC=foo /bin/sh: foo: not found Checking for a C compiler... not found. make: *** [compiler] Error 1 After: $ make CC=foo Checking for a C compiler... not found. make: *** [compiler] Error 1 Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Makefile: fix and simplify test program compilationsstefanct2011-08-181-33/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this was totally broken due to the make's shell function's temporal behavior. quote from the gnu make documentation (http://www.gnu.org/s/hello/manual/make/Shell-Function.html): "The commands run by calls to the shell function are run when the function calls are expanded" we have used the shell function to echo the test programs to a file. the file name used was equal for all tests and was overwritten for each test. the result was that all tests (in a single target?) used the last test program because the echoing of the test programs was done before all test compilations(!) see my mail for details: http://lists.gnu.org/archive/html/bug-make/2011-08/msg00010.html also the branching for testing ifeq ($(CONFIG_FT2232_SPI), yes) was unnecessarily complicated. in my approach here i am using verbatim variables (allows to define even complex test programs in the makefile without jumping through hoops) that get exported to environment variables (via "export", reference afterwards with "$$<varname>"). i have also added the missing redirection of stderr to the compiler test and changed the definition of ARCH to use simple expansion (:=). the latter is still wrong, because it uses $(CC) before we check if a compiler is installed... makes the compiler check pretty much useless. The simple expansion just reduces the number of errors printed to 1. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make flashrom build on PPC/PowerPC with just "make".uwe2011-07-291-0/+34
| | | | | | | | | | | | Build-tested in a QEMU ppc (Debian) image, and by Andrew Morgan <ziltro@ziltro.com> on real hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Andrew Morgan <ziltro@ziltro.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.4hailfinger2011-07-261-1/+1
| | | | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Autodetect target processor architecture.hailfinger2011-07-071-2/+12
| | | | | | | | | | | Enable architecture dependent compilation of individual sub-drivers for the internal programmer. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix and improve Windows/MinGW/MSYS build.uwe2011-07-031-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Makefile: Use $(OS_ARCH) to add some MinGW-specific workarounds and settings, so that a simple "make" is sufficient on MinGW (instead of manual Makefile hacking). - Explicitly set CC=gcc in the Makefile, otherwise you get an error like "cc: command not found" on MinGW. - MinGW doesn't have ffs(), use gcc's __builtin_ffs() instead. - Add /usr/local/include and /usr/local/lib to CPPFLAGS/LDFLAGS, that's where libusb-win32 and libftdi stuff is usually placed on MinGW/MSYS. - Disable serprog (no sockets) and all PCI-based programmers (no libpci) for now. That leaves dummy, ft2232_spi, and buspirate_spi enabled on MinGW per default. - serial.c: Use correct type for 'tmp', both on Windows/MinGW (DWORD) and POSIX (ssize_t). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* make Makefile's test programs safe(r)stefanct2011-06-261-5/+5
| | | | | | | | | | | | | | we don't use -W or similarly strict compiler checks (yet), but enabling its use is a good thing. if you add -W to the cflags without this patch, detection of the compiler will fail with gcc 4.4 for example, because compiling of the test program will fail due to a warning of unused arguments and -Werror. similarly the other checks involving compiling test programs would fail. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add lock printing for AMIC A25L05PT, A25L05PU, A25L10PT, A25L10PU,hailfinger2011-05-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A25L20PT, A25L20PU, A25L40PT, A25L40PU, A25L80P, A25L16PT, A25L16PU, A25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032 to a25.c. Add lock printing for Atmel AT26DF081A, AT26DF161, AT26DF161A, AT26DF321. Move Atmel AT25*/AT26* lock related functions originally added in r1115 from spi25.c to at25.c. For SPI chips the lock printing was handled by one common function, but sharing a common function which only is a big switch() statement doesn't make sense, especially if we can define lock printing functions per flash chip anyway. The printlock function pointer in struct flashchip is used to print status register and locking information, and serves as replacement for implicit status register and lock printing during probe. That code will later be changed to store locking info in a machine- accessible data structure so flashrom can handle locked regions correctly. Signed-off-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Intel NIC with parallel flash support.hailfinger2011-05-081-0/+9
| | | | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Anton Kochkov <anton.kochkov@gmail.com> Acked-by: Anton Kochkov <anton.kochkov@gmail.com> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Update port of flashrom package to Mac OS X using DirectHW:stepan2011-03-181-2/+2
| | | | | | | | | | | | http://www.coreboot.org/DirectHW Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Paul Menzel <paulepanter@users.sourceforge.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix and improve libpayload platform supportoxygene2011-03-081-2/+42
| | | | | | | | | | | | | | | - Fix various minor compile issues (eg. include necessary standard headers) - Fix compilation of libpayload code paths - Provide libpayload support in Makefile - Add make target "libflashrom.a" which links non-CLI code to static library Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Tested-with-DOS-crosscompiler-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Update the ITE IT8500 EC support to match the current state of thehailfinger2011-02-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | flashrom-chromium tree. This code has been deployed and tested to work on the Cr-48. There are a few caveats, though: - The boot BIOS straps register must be modified to select LPC. This can be done with the "select_bbs.sh" script (Install iotools at http://code.google.com/p/iotools/ before using select_bbs). - It is very important to disable power management daemons before running flashrom on this EC. I commented out the brute force method we use in the Chromium OS branch that disables powerd, since IIRC Carl-Daniel has a better approach in the works. - Due to dependencies which may be introduced by the OEM/ODM EC firmware, the code is not guaranteed to work for anything other than the Cr-48. Signed-off-by: David Hendricks <dhendrix@google.com> Carl-Daniel comments: Code is not hooked up yet because probing needs to be sorted out. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support for Angelbird Wings PCIe SSD (solid-state drive).hailfinger2011-02-041-0/+9
| | | | | | | | | | | | | | | | It uses a Marvell 88SX7042 SATA controller internally which has access to a separate flash chip hosting the option ROM. Thanks to Angelbird Ltd for sponsoring development of this driver! I expect the code to work for that SATA controller even if it is not part of the Angelbird SSD. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Winbond W39V040FB and W39V040FC.hailfinger2010-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | | Print lock status for all supported Winbond W39* chips: W39V040A, W39V040B, W39V040C, W39V040FA, W39V040FB, W39V040FC, W39V080A, W39V080FA, W39V080FA (dual mode). Fill in correct probe timing for Winbond W39V040C and W39V080FA. Please note that the W39V040B/W39V040FB pair has identical IDs, identical read/write/erase, but locking differs. Same applies to W39V040C/W39V040FC. This causes double detection on chipsets which support LPC and FWH, making flashing more difficult because the user has to select the correct chip. This is called the evil twin problem. A better evil twin handling (patch available) will resolve that problem. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Open Graphics Project development card, OGD1, as ahailfinger2010-12-031-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI flash programmer. The project is in the the process of designing and making a complete, open source, graphics card. More info at http://wiki.opengraphics.org. The first development card is a PCI add in card containing a couple of FPGAs and a couple of serial flash chips (amongst other things). The FPGAs are called XP10 and S3 (their part numbers). The XP10 contains its own flash and does not need to be programmed by flashrom - it ensures that the device can enumerate on the PCI bus without needing further configuration. The larger FPGA is the S3. This is configured from a large SPI flash (2 MBytes). The second SPI flash is used to store the VGA BIOS. It is smaller (128 KBytes). This patch adds support for programming either of the two SPI flash chips. The programmer device takes one configuration option which selects which of the two flash chips is accessed. This must be set to either "cprom" or "bprom". (The project refers to the two chips as "cprom" / "bprom", "s3" and "bios" are more readable alternatives). Add support for SST SST25VF010 (REMS). Mark SST SST25VF016B as tested for write. Signed-off-by: Mark Marshall <mark.marshall@csr.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The currently used write functions (wrappers) all use helpers whichhailfinger2010-10-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | perform the actual write (inner functions). The signature of the write wrappers is: int write_chip(struct flashchip *flash, uint8_t * buf); The signature of the inner write functions varied a lot. This patch changes them to: int write_part(struct flashchip *flash, uint8_t *src, int start, int len); Did you know that flashrom has only 8 inner write functions for all flash chips? write_page_write_jedec_common write_sector_jedec_common write_sector_28sf040 spi_chip_write_256_new spi_chip_write_1_new spi_aai_write_new write_page_82802ab write_page_m29f400bt Export all inner write functions. Change the function signature of wait_82802ab to eliminate single-use variables. Remove an error message in write_page_m29f400bt which was printed for every byte written regardless of success. Add sharplhf00l04.c to the list of flash chip drivers in the Makefile. While the functions in there are unused, I suspect we will need them later, and by hooking the file up we ensure that compilation won't break. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.3.hailfinger2010-10-081-1/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* CONFIG_BITBANG_SPI was not selected if CONFIG_NICINTEL_SPI was on byhailfinger2010-10-081-15/+15
| | | | | | | | | | | | | | | | default. Wiki output was missing all flash chips if CONFIG_INTERNAL was not selected. Use correct type for toupper()/tolower()/isspace() functions. Specify software requirements in a generic way. Non-x86 compilation does not work with the default programmer set, so list the make parameters which result in a working build. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The Direct I/O library for Mac OS X is now called DirectHW to make surehailfinger2010-10-061-0/+1
| | | | | | | | | | | people can find it via an internet search. DirectIO was a generic name for a concept and thus not a good distinguisher for a library. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Intel Gigabit NIC SPI flashing support.uwe2010-09-031-0/+13
| | | | | | | | | | | | | | | | | | | | | | Tested on a 82541PI (0x8086, 0x107c) using 32-bit hardware. The last line in nicintel_request_spibus() could be changed so that FL_BUSY is used instead. Shortened sample log: [...] Found "Intel 82541PI Gigabit Ethernet Controller" (8086:107c, BDF 01:03.0). Found chip "ST M25P10.RES" (128 KB, SPI) at physical address 0xfffe0000. Multiple flash chips were detected: M25P05.RES M25P10.RES Please specify which chip to use with the -c <chipname> option. [...] Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Compile gfxnvidia by default, but disallow write/erase.hailfinger2010-07-291-2/+2
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashinghailfinger2010-07-281-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | support. Huge thanks go to Michael Karcher for reverse engineering the interface and to Johannes Sjölund for testing the first iterations of my patch on his hardware until it worked. Thanks to the following testers of the patch: * MCP61, 10de:03e0, LPC OK, ECS Geforce6100SM-M, Andrew Cleveland * MCP61, 10de:03e0, LPC OK, Biostar NF520-A2 NF61D-A2, Vitaliy Buchynskyy * MCP65, 10de:0441, SPI OK, MSI MS-7369 K9N Neo-F v2, Kjell Braden * MCP65, 10de:0441, SPI OK, MSI MS-7369, Wolfgang Schnitker * MCP65, 10de:0441, SPI OK, MSI MS-7369, Johannes Sjölund * MCP65, 10de:0441, SPI OK, MSI MS-7369, Melchior Franz * MCP78S, 10de:075c, SPI OK, Asus M3N78 PRO, Brad Rogers * MCP78S, 10de:075c, SPI OK, Asus M3N78-VM, Marcel Partap * MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Kimmo Vuorinen * MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Vikram Ambrose * MCP79, 10de:0aad, SPI OK, Acer Aspire R3600, Andrew Morgan * MCP79, 10de:0aae, LPC ??, Lenovo Ideapad S12 laptop, Christian Schmitt * MCP79, 10de:0aae, SPI OK, Apple iMac9,1 Mac-F2218EA9, David "dledson" flashrom will refuse to write/erase for safety reasons if MCP6x/MCP7x SPI is detected. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for RayeR SPIPGM hardware as described inhailfinger2010-07-211-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://rayer.ic.cz/elektro/spipgm.htm To use the RayeR driver, run flashrom -p rayer_spi -V Known bugs/limitations: - Won't compile/work on non-x86 architectures. - Will always use direct port I/O access. Log follows: flashrom v0.9.2-r1039 on MS-DOS 7 (i686), built with libpci 3.1.5, GCC 4.3.2, little endian Calibrating delay loop... OK. Initializing rayer_bitbang_spi programmer Using port 0x378 as I/O base for parallel port access. ... Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 ... Found chip "Macronix MX25L1605" (2048 KB, SPI) at physical address 0xffe00000. ... No operations were specified. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Martin Rehak <rayer@seznam.cz> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add OpenBSD support.hailfinger2010-07-021-0/+8
| | | | | | | | | | | | | | | Add a requirements section to the man page which lists the needed access permissions for each programmer. This feature needs my pciutils/libpci 8/16-bit write emulation patch at http://marc.info/?l=openbsd-ports&m=127780030728045 titled [PATCH] Fix pciutils non-32bit PCI write on OpenBSD Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stuart Henderson <sthen@openbsd.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Work around shadowing warnings in libpci headers. This is needed forhailfinger2010-06-251-1/+3
| | | | | | | | | | | warning-free compilation on older gcc versions (3.x and probably older). Such a gcc version is the default on i386 OpenBSD. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stuart Henderson <sthen@openbsd.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Detect incompatible CONFIG_FOO=yes for the specified target and refusehailfinger2010-06-141-5/+35
| | | | | | | | | | | | | | to compile with a meaningful error message. Set the default for incompatible CONFIG_FOO to no. Just running "make" should result in a a build which compiles the common subset of available and working features. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer+lists.flashrom@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Handle OS where executables have a hardcoded suffix, e.g. DOS with .exehailfinger2010-06-141-19/+21
| | | | | | | | | | | This ensures that any temp files in the configure/check step of the Makefile are removed correctly. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer+flashrom@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* We already have NEED_PCI in the Makefile to link in PCI support. Addhailfinger2010-06-141-12/+12
| | | | | | | | | | | | | NEED_SERIAL and NEED_NET to decouple individual drivers from compilation and linking decisions. Move libgetopt from a DOS+PCI dependency to a DOS dependency to fix linking on DOS if no driver requiring PCI is enabled. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1044 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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