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* Fix wrong density encoding on Intel Silvermont.stefanct2015-01-051-11/+7
| | | | | | | | | | | | | | Silvermont (Bay Trail, Rangeley, Avoton) seems to still use the old density encoding with 3 bits per chip. Documentation is unavailable (held concealed by Intel) but thanks to the efforts of Tai-Hong (Type) Wu the layout is clear now. This patch is based on his one but solves the issue differently thus reducing the code complexity. Signed-off-by: Tai-Hong Wu <thwu@lunartoday.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel Wildcat Point PCH.stefanct2014-08-201-1/+1
| | | | | | | | | | | The Wildcat Point PCH can be paired with Broadwell or Haswell. This patch was essentially backported from ChromiumOS commit 9bd2af8. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refine Flash Component descriptor handling.stefanct2014-08-201-7/+34
| | | | | | | | | | | | | | | Possible values as well as encodings have changed in newer chipsets as follows. - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all operations - Since Cougar Point the chipsets support dual output fast reads (encoded in bit 30). - Flash component density encoding has changed from 3 to 4 bits with Lynx Point, currently allowing for up to 64 MB chips. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 13.stefanct2012-07-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested Mainboards: OK: - ASRock A780FullHD http://www.flashrom.org/pipermail/flashrom/2012-July/009599.html - ASRock 880G Pro3 http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html - ASRock N61P-S http://www.flashrom.org/pipermail/flashrom/2012-May/009316.html - ASUS M2N68-VM http://www.flashrom.org/pipermail/flashrom/2012-May/009334.html - ASUS M3N78 PRO http://www.flashrom.org/pipermail/flashrom/2012-July/009519.html - ASUS M4N68T V2 http://www.flashrom.org/pipermail/flashrom/2012-May/009277.html - ASUS M5A78L-M LX reported by clavile on IRC - ASUS P8P67 PRO (rev. 3.0) http://www.flashrom.org/pipermail/flashrom/2012-April/009188.html - ASUS P8Z68-V reported by Kano on IRC http://paste.flashrom.org/view.php?id=1232 - ASUS SABERTOOTH 990FX http://paste.flashrom.org/view.php?id=1214 - Dell Inspiron 1420 http://www.flashrom.org/pipermail/flashrom/2012-May/009196.html - ECS GF8200A http://www.flashrom.org/pipermail/flashrom/2012-May/009256.html - GIGABYTE GA-H61M-D2H-USB3 http://www.flashrom.org/pipermail/flashrom/2012-May/009333.html - MSI MS-7250 (K9N SLI (rev 2.1)) http://www.flashrom.org/pipermail/flashrom/2012-June/009436.html - MSI MS-7676 (Z68MA-G45 (B3)) http://www.flashrom.org/pipermail/flashrom/2012-June/009424.html - Palit N61S http://www.flashrom.org/pipermail/flashrom/2012-May/009212.html NOT OK: - ASRock H61M-ITX http://www.flashrom.org/pipermail/flashrom/2012-May/009224.html - Dell Latitude E6520 http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html - Dell Vostro 3700 http://www.flashrom.org/pipermail/flashrom/2012-May/009197.html - Intel DH61AG http://www.flashrom.org/pipermail/flashrom/2012-June/009417.html - Intel DQ965GF http://www.flashrom.org/pipermail/flashrom/2012-May/009295.html - HP/Compaq 8100 Elite CMT PC (304Bh) http://paste.flashrom.org/view.php?id=1182 - HP Z400 Workstation (0AE4h) http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html - Supermicro X9DR3-F http://www.flashrom.org/pipermail/flashrom/2012-June/009422.html Tested flash chips: - mark AMIC A25L032 as TEST_OK_PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-June/009363.html - mark Atmel AT25DF321A as TEST_OK_PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2012-July/009492.html - mark Atmel AT26DF161 as TEST_OK_PR (+PR) http://www.flashrom.org/pipermail/flashrom/2012-June/009350.html - mark Eon EN25QH16 as TEST_OK_PR (+PR) http://www.flashrom.org/pipermail/flashrom/2012-July/009566.html - mark SST SST39VF010 as TEST_OK_PREW (+W) http://www.flashrom.org/pipermail/flashrom/2012-June/009425.html - mark ST M25P64 as TEST_OK_PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html Tested chipset enables: - Intel 3420 http://www.flashrom.org/pipermail/flashrom/2012-May/009332.html - Add board enable for ASUS P5GD2-X lspci: http://paste.flashrom.org/view.php?id=1234 write: http://paste.flashrom.org/view.php?id=1240 Miscellaneous - Reorder some boards in print.c. - Remove broken abit URLs. - Whitespace changes. - Fix the maximum number of southbridge straps in the ICH descriptor structs. - Refine documentation regarding ICH region lock bits. - Demote verbosity of ICH Opcode reprogramming to -VV. - Exclude Pony-SPI for DOS targets (missing serial support). Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add ich_descriptor_tool to decode all flash descriptors stored in a flash ↵stefanct2011-12-241-1/+328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | dump file This patch adds an external utility that shares most of the existing descriptor decoding source code. Additionally to what is available via FDOC/FDOD this allows to access: - the softstraps which are used to configure the chipset by flash content without the need for BIOS routines. on ICH8 it is possible to read those with FDOC/FDOC too, but this was removed in later chipsets. - the ME VSCC (Vendor Specific Component Capabilities) table. simply put, this is an SPI chip database used to figure out the flash's capabilities. - the MAC address stored in the GbE image. Intel thinks this information should be confidential for ICH9 and up, but references some tidbits in their public documentation. This patch includes the human-readable information for ICH8, Ibex Peak (5 series) and Cougar Point (6 series); the latter two were obtained from leaked "SPI Flash Programming Guides" found by google. Data regarding ICH9 and 10 is unknown to us yet. It can probably found in: "Intel® ICH7, ICH8, ICH9 and ICH10 — SPI Family Flash Programming Guide" Information regarding the upcoming Panther Point chipset is also not included. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Matthias Wenzel <bios@mazzoo.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: use a variable to distinguish ich generations instead of ↵stefanct2011-11-061-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_programmer->type The type member is enough most of the time to derive the wanted information, but - not always (e.g. ich_set_bbar), - only available after registration, which we want to delay till the end of init, and - we really want to distinguish between chipset version-grained attributes which are not reflected by the registered programmer. Hence this patch introduces a new static variable which is set up early by the init functions and allows us to get rid of all "switch (spi_programmer->type)" in ichspi.c. We reuse the enum introduced for descriptor mode for the type of the new variable. Previously magic numbers were passed by chipset_enable wrappers. Now they use the enumeration items too. To get this working the enum definition had to be moved to programmer.h. Another noteworthy detail: previously we have checked for a valid programmer/ich generation all over the place. I have removed those checks and added one single check in the init method. Calling any function of a programmer without executing the init method first, is undefined behavior. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: add (partially) dead support code for Intel Hardware Sequencingstefanct2011-10-201-0/+1
| | | | | | | | | | This was done to ease the review. Another patch will hook up (and explain) this code later. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDODstefanct2011-09-151-0/+260
based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for correct layout before taking any action on runtime. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1