summaryrefslogtreecommitdiff
path: root/ichspi.c
Commit message (Collapse)AuthorAgeFilesLines
* Proper error handling for ICH/VIA SPI:hailfinger2011-03-171-22/+80
| | | | | | | | | | | | | | | Use 16-bit values for bit masks in 16-bit registers. Check for SPI Cycle In Progress and wait up to 60 ms. Do not touch reserved bits. Reduce SPI cycle timeout from 60 s to 60 ms. Clear transaction errors caused by our own SPI accesses. Add better debugging in case the hardware misbehaves. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch reduces the stack usage by declaring 'const' stack variableskrause2011-01-171-2/+2
| | | | | | | | | | | | | | as 'static const' so they end up in the .rodata section instead of being copied from there to the stack for every invocation of the corresponding function. As a plus we end up in having a smaller binary as the "copy from .rodata to stack" code isn't emitted by the compiler any more (roughly -100 bytes). Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Dump all VIA SPI registers like for ICH7.hailfinger2010-11-241-7/+49
| | | | | | | | | | | Handle BBAR on VIA. Handle SPI lockdown on VIA. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Implement on-the-fly reprogramming of the ICH SPI OPCODE table.hailfinger2010-10-051-20/+79
| | | | | | | | Signed-off-by: Helge Wagner <helge.wagner@ge.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel 5 Series / 3400 Series chipsetsmkarcher2010-08-111-1/+3
| | | | | | | | | | | (At least) for the QM57 which i have tested an additional patch was needed as some reserved bits in the "Software Sequencing Flash Control Register" (SSFC) needs to be programmed to 1 in the QM57. Signed-off-by: Helge Wagner <helge.wagner@ge.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split off programmer.h from flash.h.hailfinger2010-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move Intel SPI initialisation to ichspi.cmkarcher2010-07-221-3/+210
| | | | | | | | | | | Smarter version could decide whether SPI is vital or not depending on straps. Straps are currently implemented for ICH7. EP80579 is in the comment, PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI". Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* We have a generic unlocking infrastructure. Use it for SPI chips.hailfinger2010-07-141-1/+0
| | | | | | | | | | Actually check if the unlock worked instead of just assuming it worked. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert SPI chips to partial write, but wrap the write functions in ahailfinger2010-07-141-23/+2
| | | | | | | | | | | | | | compat layer to allow converting the rest of flashrom later. I actually have patches for most of the remaining conversion, but I wanted to get this out and reviewed first. Tested on Intel NM10 by David Hendricks. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kill global variables, constants and functions if local scope suffices.hailfinger2010-07-031-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | Constify variables where possible. Initialize programmer-related variables explicitly in programmer_init to allow running programmer_init from a clean state after programmer_shutdown. Prohibit registering programmer shutdown functions before init or after shutdown. Kill some dead code. Rename global variables with namespace-polluting names. Use a previously unused locking helper function in sst49lfxxxc.c. This is needed for libflashrom. Effects on the binary size of flashrom are minimal (300 bytes shrinkage), but the data section shrinks by 4384 bytes, and that's a good thing if flashrom is operating in constrained envionments. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ICH SPI can enforce address restrictions for all accesses which take anhailfinger2010-05-281-1/+49
| | | | | | | | | | | | | | | address (well, it could if the chipset implementation was not broken). Since exploiting the broken implementation is harder than conforming to the address restrictions wherever possible, conform to the address restrictions instead. This patch eliminates a lot of transaction errors people were seeing on chip probe. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Handle the following architectures in generic flashrom code:hailfinger2010-05-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Misha Manulis for testing early versions of this patch on PowerPC (big endian) with the satasii programmer. Thanks to Segher Boessenkool for design review and for helping out with compiler tricks and pointing out that we need eieio on PowerPC. Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). Thanks to Uwe Hermann for compile and runtime testing on x86_64. DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH! This patch only provides the infrastructure, but does not convert any drivers, so flashrom will compile, but it won't do the right thing on non-x86 platforms. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Every SPI programmer driver had its own completely different chip writehailfinger2010-05-211-36/+10
| | | | | | | | | | | | | | | | implementation, and all of them were insufficiently commented. Create spi_write_chunked as a copy of spi_read_chunked and convert all SPI programmers to use it. No functional changes except: - Bus Pirate uses 12 Byte writes instead of 8 Byte writes - SB600 uses 5 Byte writes instead of 1 Byte writes Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* convert programmer print messages to msg_p*snelson2010-05-071-44/+35
| | | | | | | | | | | | convert general print messages to msg_g* a few fixes as suggested by Carl-Daniel Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Polish the flashrom code comments and outputs a bit.uwe2010-03-251-1/+1
| | | | | | | | | | | | | - Fix a number of typos (found via ispell). - Use correct vendor names (as per their websites) consistently. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split spi.c into programmer and chip codesnelson2010-02-261-0/+1
| | | | | | | | | | | | | | | | | | | | | Remove chipdriver.h include from flash.h Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This megapatch rewrites substantial parts of ICH SPI to actually do whathailfinger2010-02-111-53/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the SPI layer wants instead of its own weird idea about commands (running unrequested commands, running modified commands). Besides that, there is a fair share of cleanups as well. - Add JEDEC_EWSR (Enable Write Status Register) to default commands. - Mark a no longer used opcode/preopcode table as unused. - Declare all commands as non-atomic/standalone by default. The ICH SPI driver has no business executing commands (preopcodes) automatically if they were not requested. - Automatically adjust preopcode/opcode pairings (like WREN+ERASE) based on what the SPI layer requested. The ICH SPI driver has no business executing altered opcode pairs as it sees fit. - Fix incomplete initialization in the case of a locked down chipset. Leaving the first 4 opcodes with uninitialized pairings had unpredictable results. - switch() exists for a reason. Nested if() checking on the same variable is an interesting style. - Actually check if the requested readcnt/writecnt for a command is supported by the hardware instead of delivering corrupt/incomplete commands and data. - If a command has unsupported readlen/writelen, complain loudly to the user. - Use find_opcode instead of open-coding the same stuff in a dozen variations. - Introduce infrastructure for updating the command set of unlocked chipsets on the fly. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Programmer debug messages during programmer init/shutdown are usefulhailfinger2010-01-071-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | because they print hardware settings and desired configuration. They help in getting a quick overview of hardware and software state on startup and shutdown. Programmer debug messages during flash chip access are mostly a distraction in logs and should only be enabled if someone is having problems which are suspected to stem from a programmer hardware or programmer software bug. Disable those messages by default, they can be reenabled by #define COMM_DEBUG in the affected programmer file. An added benefit is a tremendous size reduction in verbose probe/read/write/erase logs because only flash chip driver messages remain. In some cases, logs will shrink from 65 MB to 10 kB or less. The right(tm) fix would be two different debug levels (DEBUG and SPEW) and the ability to differentiate between programmer debug messages and flash chip debug messages. Until the design for the message printing infrastructure is finished, this is the best stop-gap measure we can get. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audioahcked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kill hardcoded block erase on ICH SPI.hailfinger2009-11-251-11/+7
| | | | | | | | | | | | | The existing code does not work for all SPI chips, and it just was a band-aid to cope with locked down chipsets back in a time when there was no eraseblock infrastructure. Basically, this unbreaks a few SPI chips on ICH. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Maciej Pijanka <maciej.pijanka@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Since we don't have any debug level printing infrastructure yet, Ihailfinger2009-10-221-4/+1
| | | | | | | | | | | | | | | | propose to kill the obnoxious debug message in ichspi.c which was added to check for correct PREOP handling. We know the code works fine (after getting a few reports over 100 MB long) and there's no point in keeping it around anymore. If there is any desire, we can reinstate it as print_spew or whatever once the debug level infrastructure is merged, but at that point we probably just are happy that the debug output isn't there anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The current ICH SPI preop handling is a hack which spews lots ofhailfinger2009-09-181-14/+21
| | | | | | | | | | | | | | | | | | warnings, but still yields correct results. With the multicommand infrastructure I introduced in r645, it became possible to integrate ICH SPI preopcodes cleanly into the flashrom design. The new code checks for every opcode in a multicommand array if it is a preopcode. If yes, it checks if the next opcode is associated with that preopcode and in that case it simply runs the opcode because the correct preopcode will be run automatically before the opcode. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: FENG Yu Ning <fengyuning1984@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Standardize on using __func__ instead of __FUNCTION__.uwe2009-09-021-4/+4
| | | | | | | | | | | | | | | | | The __func__ variant is standardized in C99 and recommended to be used instead of __FUNCTION__ in the gcc info page. Only _very_ old versions of gcc did not know about __func__, but we've been using both __func__ and __FUNCTION__ for a long while now, and nobody complained about this, so all our users seem to use recent enough compilers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove unnecessary #include files.hailfinger2009-08-091-1/+0
| | | | | | | | | | | Serprog compilation is now controlled by a Makefile variable. Replace munmap with physunmap where appropriate. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Replace most of the switch cases in the spi code with lookup on a structhailfinger2009-07-221-0/+20
| | | | | | | | | | | | | | | | instead. This brings the SPI code in line with the generic programmer infrastructure. This patch is a reworked version of a patch by Jakob Bornecrantz. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use a distinct return code for SPI commands with unsupported/invalidhailfinger2009-07-141-3/+10
| | | | | | | | | | | | | length. Some drivers support only a few combinations of read/write length and return error otherwise. Having a distinct return code for this error means we can handle it in upper layers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add SPI multicommand infrastructure.hailfinger2009-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> Tested-by: Jakob Bornecrantz <wallbraker@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Check result of all SPI erase functions.hailfinger2009-06-241-1/+1
| | | | | | | | | | | | | | | Since block erase functions do not know the block length (it's not specified in any standard), block erase functions now get an additional parameter blocklen. This enables flashrom to verify the erase result for block erase functions at correct boundaries. Tested by Uwe on SB600. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use spi_nbyte_program in ichspi.c.hailfinger2009-06-171-20/+7
| | | | | | | | | | This shortens the code a lot and makes it more readable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch gives us arbitrary range reads at byte boundaries for everyhailfinger2009-06-161-2/+2
| | | | | | | | | | | | | | single chip supported by flashrom. That means you can tell flashrom to read exactly bytes 12345-56789 (start 12345, length 44445) and it will not fetch a single byte more. Uwe tested this on one LPC, one SPI, and one parallel flash board. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Every SPI host controller implemented its own way to read flash chips.hailfinger2009-06-131-45/+2
| | | | | | | | | | | | | | | | | | | | | | | This was partly due to a design problem in the abstraction layer. There should be exactly two different functions for reading SPI chips: - memory mapped reads - SPI command reads. Each of them should be contained in a separate function, optionally taking parameters where needed. This patch solves the problems mentioned above, shortens the code and makes the code logic a lot more obvious. Since open-coding the min() function leads to errors, include it in this patch as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add external programmer delay functions so external programmers canhailfinger2009-06-051-2/+2
| | | | | | | | | | | handle the delay on their own if needed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Urja Rannikko <urjaman@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add bus type annotation to struct flashchips. Right now, the annotationhailfinger2009-05-311-14/+14
| | | | | | | | | | | | | | | | | | | | only differentiates between SPI and non-SPI. Anyone who knows more about a specific flash chip should feel free to update it. The existing flashbus variable was abused to denote the SPI controller type. Use an aptly named variable for that purpose. Once this patch is merged, the chipset/programmer init functions can set supported flash chip types and flashrom can automatically select only matching probe/read/erase/write functions. A side benefit of that will be the elimination of the Winbond W29EE011 vs. AMIC A49LF040A conflict. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use REMS instead of RES in the ICH SPI default opcode table.hailfinger2009-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RES is Read Electronic Signature (1 Byte, identical for different chips) REMS is Read Electronic Manufacturer Signature (2 Bytes, mostly unique) RDID is Read JEDEC ID (3 bytes, unique) Of the chips which don't support RDID, a sizable portion supports REMS which gives us both a manufacturer ID and a device ID. This is clearly superior to having only a device ID (the RES case) which has multiple documented collisions. The RES/REMS problem is aggravated by inconsistent naming in vendor data sheets. What's in a name? Considering that we have 1-byte IDs, 2-byte IDs and 3+byte IDs with varying names but mostly consistent opcodes, it makes sense to set our own standard about how the opcodes are called. The best way forward would be to have the ICH SPI driver reprogram the opcode menu on the fly if the opcode menu doesn't contain the requested opcode and the opcode menu is not locked. Until that happens, this patch improves detection accuracy by a factor of 256 for some chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Uwe Hermann with the flash chip "SST SST25VF040.REMS". Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use accessor functions for MMIO. Some MMIO accesses used volatile,hailfinger2009-05-171-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | others didn't (and risked non-execution of side effects) and even with volatile, some accesses looked dubious. Since the MMIO accessor functions and the onboard flash accessor functions are functionally identical (but have different signatures), make the flash accessors wrappers for the MMIO accessors. For some of the conversions, I used Coccinelle. Semantic patch follows: @@ typedef uint8_t; expression a; volatile uint8_t *b; @@ - b[a] + *(b + a) @@ expression a; volatile uint8_t *b; @@ - *(b) |= (a); + *(b) = *(b) | (a); @@ expression a; volatile uint8_t *b; @@ - *(b) = (a); + mmio_writeb(a, b); @@ volatile uint8_t *b; @@ - *(b) + mmio_readb(b) @@ type T; T b; @@ ( mmio_readb | mmio_writeb ) (..., - (T) - (b) + b ) Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Uwe tested read, write, erase with this patch on a random board to make sure nothing breaks. Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Eliminate all 'inline's from the flashrom code. They serve prettyuwe2009-05-161-6/+6
| | | | | | | | | | | | | much no purpose, compilers can optimize pretty much all of what we might mark as inline anyway, _and_ inlines are not enforced in any way by the compiler either. They're totally unneeded. Kill them. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Drop unused/duplicated #includes and some dead code (trivial).uwe2009-05-161-3/+0
| | | | | | | | | | | Build-tested on 32bit x86. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* There are various reasons why a SPI command can fail. Among others, Ihailfinger2009-05-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | have seen the following problems: - The SPI opcode is not supported by the controller. ICH-style controllers exhibit this if SPI config is locked down. - The address in in a prohibited area. This can happen on ICH for any access (BBAR) and for writes in chipset write protected areas. - There is no SPI controller. Introduce separate error codes for unsupported opcode and prohibited address. Add the ability to adjust REMS and RES addresses to the minium supported read address with the help of spi_get_valid_read_addr(). That function needs to call SPI controller specific functions like reading BBAR on ICH. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Trim default ICH SPI delay from 1000 to 10 microseconds. Since manyhailfinger2009-05-091-4/+4
| | | | | | | | | | | | | | | | | commands take around 10 microseconds to complete, it is totally pointless to wait for 1000 microseconds before checking the status again. This patch is tested and reduced write time on ICH7 with SST25VF080B from over one hour to 62 seconds. Thanks to Ali Nadalizadeh for testing! Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Chips like the SST SST25VF080B can only handle single byte writeshailfinger2009-05-091-1/+1
| | | | | | | | | | | | | | | | | | | outside AAI mode. Change SPI architecture to handle 1-byte chunk chip writing differently from 256-byte chunk chip writing. Annotate SPI chip write functions with _256 or _1 suffix denoting the number of bytes they write at maximum. The 1-byte chunk writing is cut-n-pasted to different SPI drivers right now. A later patch can move them to the generic spi_chip_write_1. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4117uwe2009-04-151-7/+5
| | | | | | | | | | | Some coding style and consistency fixes (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3918stuge2009-01-261-1/+0
| | | | | | | | | | | | flashrom: Fix one dead increment and one dead assignment as found by clang. Thanks Patrick! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3862stuge2009-01-151-0/+1
| | | | | | | | | | flashrom: Add ICH opcode debugging. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3814stuge2008-12-151-27/+30
| | | | | | | | | | | | | | | | | | | | | * add a generic preop-opcode-pair table. * rename ich_check_opcodes to ich_init_opcodes. * let ich_init_opcodes do not need to access flashchip structure: . move the definition of struct preop_opcode_pair to a better place . remove preop_opcode_pairs from 'struct flashchip' . modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure * call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works. * fix a coding style mistake. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3805stepan2008-12-081-0/+134
| | | | | | | | | | | | Generates OPCODES struct from the ICH7/ICH9/VIA chipset if its SPI configuration is locked down. Signed-off-by: FENG yu ning <fengyuning1984@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3758hailfinger2008-11-181-9/+5
| | | | | | | | | | | | | | Currently flashrom assumes every vendor BIOS shares our view about which SPI opcodes should be placed in which location. Move to a less optimistic implementation and actually use the generic SPI read functions. They're useful for abstracting exactly this stuff and that makes them the preferred choice. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3722hailfinger2008-11-031-16/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add additional SPI sector erase and chip erase command functions to flashrom. Not all chips support all commands, so allow the implementer to select the matching function. Fix a layering violation in ICH SPI code to be less bad. Still not perfect, but the new code is shorter, more generic and architecturally more sound. TODO (in a separate patch): - move the generic sector erase code to spi.c - decide which erase command to use based on info about the chip - create a generic spi_erase_all_sectors function which calls the generic sector erase function Thanks to Stefan for reviewing and commenting. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3721stepan2008-11-021-15/+45
| | | | | | | | | | | | Drop nr/opcode_index parameter from run_opcode and search the opmenu for the opcode instead. This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3669uwe2008-10-181-12/+12
| | | | | | | | | | | Coding-style fixes for flashrom, partly indent-aided (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3417stuge2008-07-071-3/+3
| | | | | | | | | | flashrom: Trivial indent fix in ichspi.c Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3401stepan2008-06-301-53/+54
| | | | | | | | | | | | | | | | | | | | | First attempt to clean up SPI probing and create a common construct: the flash bus. At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
View Lorry Controller Status