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* add a bunch of new/tested stuff and various small changes 4stefanct2011-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add Asus E35M1-I DELUXE to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006918.html - add Asus M3A to boards_known http://www.flashrom.org/pipermail/flashrom/2011-July/007085.html - add Freetech P6F91i to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html - add GA-M720-US3 to boards_known http://www.flashrom.org/pipermail/flashrom/2011-July/007096.html - add GA-MA770-UD3 (rev. 2.1) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006879.html - add GA-965GM-S2 to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006746.html - add HP xw4400 (0A68h) to boards_known http://paste.flashrom.org/view.php?id=686 - add MSI MS-6566 (845 Ultra-C) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/006908.html - add MSI MS-7698 (E350IA-E45) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-June/007003.html - add PCCHIPS M863G (V5.1A) to boards_known http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html - modify the X8SIE entry in boards_known with the information from "fuzzy" http://paste.flashrom.org/view.php?id=669 - mark W29C020(C)/W29C022 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-June/006800.html - mark W49V002A as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007084.html - mark M25P128 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-June/006843.html - mark SST39SF010A as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007115.html - correct entries for GA-K8NS Pro-939 (was ultra before. thanks uwe!) - another tiny fix for "a small fix"/r1321 Without this you will get broken bus names "Unknow" and "Non-SP". Note to self: don't self-ack even fairly trivial patches. - fix spew output of spi_rems in spi25.c - add URL to ASUS M3A76-CM - rename all Winbond W25x chips to W25X - fixes some common misspellings/typos in comments: lenght->length 2 ocassional->occasional 1 unsucessfull->unsuccessful 1 upto->up to 5 the patch for M25P128 is Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> the typos are Signed-off-by: Peter Huewe <peterhuewe@gmx.de> everything else is Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Erase functions are no longer called from chip drivers and thus theirhailfinger2011-06-261-24/+6
| | | | | | | | | | | | | internal erase verification can be moved to generic code. This also makes it easier to skip the verify step if desired and to differentiate between failed command submission and failed erase verification. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* tiny fix for a small fixstefanct2011-05-281-3/+1
| | | | | | | | | | | | | there was one line break added too much in the previous commit, sorry. the probing functions need to output at least one '\n' for satisfactory output. that means even in error cases they have to do that. OTOH they should not output a sequence of "\n\n" because it would distort the verbose probing output with empty lines. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* small fixesstefanct2011-05-281-5/+15
| | | | | | | | | | | - missing spaces in code and output - improved documentation/naming/output - missing line breaks in spi probing functions Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add lock printing for AMIC A25L05PT, A25L05PU, A25L10PT, A25L10PU,hailfinger2011-05-191-258/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A25L20PT, A25L20PU, A25L40PT, A25L40PU, A25L80P, A25L16PT, A25L16PU, A25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032 to a25.c. Add lock printing for Atmel AT26DF081A, AT26DF161, AT26DF161A, AT26DF321. Move Atmel AT25*/AT26* lock related functions originally added in r1115 from spi25.c to at25.c. For SPI chips the lock printing was handled by one common function, but sharing a common function which only is a big switch() statement doesn't make sense, especially if we can define lock printing functions per flash chip anyway. The printlock function pointer in struct flashchip is used to print status register and locking information, and serves as replacement for implicit status register and lock printing during probe. That code will later be changed to store locking info in a machine- accessible data structure so flashrom can handle locked regions correctly. Signed-off-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* kill central list of SPI programmersmkarcher2011-05-111-2/+2
| | | | | | | | | | | | | | | | | | Remove the array spi_programmer, replace it by dynamic registration instead. Also initially start with no busses supported, and switch to the default non-SPI only for the internal programmer. Also this patch changes the initialization for the buses_supported variable from "everything-except-SPI" to "nothing". All programmers have to set the bus type on their own, and this enables register_spi_programmer to just add the SPI both for on-board SPI interfaces (where the internal programmer already detected the other bus types), as well as for external programmers (where we have the default "none"). Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch reduces the stack usage by declaring 'const' stack variableskrause2011-01-171-9/+9
| | | | | | | | | | | | | | as 'static const' so they end up in the .rodata section instead of being copied from there to the stack for every invocation of the corresponding function. As a plus we end up in having a smaller binary as the "copy from .rodata to stack" code isn't emitted by the compiler any more (roughly -100 bytes). Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix internal offset calculations for SPI BYTE PROGRAM and SPI AAI PROGRAM.hailfinger2010-10-271-4/+12
| | | | | | | | | | | | | | | | | The bug was invisible so far because we always started at offset 0. The pending partial write patch uses nonzero start offsets and trips over this bug. Clarify a few comments in IT87 SPI. Thanks to Idwer Vollering for reporting write breakage with my latest partial write patch. This should fix the underlying problem. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Switch all flash chips to partial write.hailfinger2010-10-131-18/+24
| | | | | | | | | | | | | | | | The inner write functions which handle partial write are renamed to the original name of their wrappers. The write wrappers are removed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Tested-by: Andrew Morgan <ziltro@ziltro.com> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Idwer Vollering <vidwer@gmail.com> Tested-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* flashrom had an implicit erase-on-write for most flash chip andhailfinger2010-10-081-16/+0
| | | | | | | | | | | | | | | | | programmer drivers, but it was not entirely consistent. Some drivers had their own hand-rolled partial update functionality which made handling partial updates from generic code impossible. Move implicit erase out of chip drivers, and kill some dead erase functions at the same time. A full chip erase is now performed in the generic code for all flash chips on write, and after that the whole chip is written. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* SPI write status register (WRSR) may take longer than 100 ms, and ithailfinger2010-10-081-4/+36
| | | | | | | | | | | makes sense to poll for completion in 10 ms steps until 5 s are over. This patch complements r1115. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Joshua Roys <roysjosh@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use AAI write for SST SST25VF032B.hailfinger2010-10-051-1/+15
| | | | | | | | | | | | | Speedup from 228 to 113 seconds. Use page (256 byte) write for SST SST25VF064C. Speedup from 3091 to 123 seconds. Signed-off-by: Helge Wagner <helge.wagner@ge.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch changes the prefix of chip constant #defines in the following way:mhm2010-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | AM_* -> AMD_AM* AT_* -> ATMEL_AT* EN_* -> EON_EN* HY_* -> HYUNDAI_HY* MBM* -> FUJITSU_MBM* MX_ID -> MACRONIX_ID MX_* -> MACRONIX_MX* PMC_* -> PMC_PM* SST_* -> SST_SST* It leaves the Intel #defines alone because there is another pending patch for that: http://patchwork.coreboot.org/patch/1937/ Some background discussion here: http://www.flashrom.org/pipermail/flashrom/2010-July/004059.html Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1175 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add detailed status register printing and unlocking for all ATMEL AT25*hailfinger2010-07-291-14/+312
| | | | | | | | | | | | | | | | | chips. Add support for Atmel AT25DF081A and AT25DQ161. Some chips require EWSR before WRSR, others require WREN before WRSR, and some support both variants. Add feature_bits to select the correct SPI command, and default to EWSR. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Steven Rosario Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split off programmer.h from flash.h.hailfinger2010-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the following AMIC SPI chips:hailfinger2010-07-221-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | http://www.amictechnology.com/pdf/A25L20P.pdf covers: AMIC A25L05PT AMIC A25L05PU AMIC A25L10PT AMIC A25L10PU AMIC A25L20PT AMIC A25L20PU http://www.amictechnology.com/pdf/A25L16P.pdf covers: AMIC A25L16PT AMIC A25L16PU Clarify the situation surrounding the A25L40PT and A25L40PU chips which share the same RDID values, despite the fact that their erase block layouts are different. Rudolf Marek tested and confirmed the distinct erase block layouts of these chips. Add a pretty-printer for the AMIC SPI chip status register Add a generic AMIC chip type. Signed-off-by: Daniel Lenski <dlenski@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* We have a generic unlocking infrastructure. Use it for SPI chips.hailfinger2010-07-141-15/+6
| | | | | | | | | | Actually check if the unlock worked instead of just assuming it worked. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert SPI chips to partial write, but wrap the write functions in ahailfinger2010-07-141-25/+35
| | | | | | | | | | | | | | compat layer to allow converting the rest of flashrom later. I actually have patches for most of the remaining conversion, but I wanted to get this out and reviewed first. Tested on Intel NM10 by David Hendricks. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The SPI opcode 0xd8 is not a chip erase opcode on any chip out there.hailfinger2010-06-201-23/+0
| | | | | | | | | | | | | Besides that, the function as implemented just walks the chip and ignores sector sizes. Sector erase with SPI opcode 0xd8 is of course still supported. Kill a declaration for a nonexisting function while we're at it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Modernize SPI AAI code, blacklist IT87 SPI for AAI, allow AAI to runhailfinger2010-06-201-13/+64
| | | | | | | | | | | without warnings on ICH/VIA SPI. Add some code to make conversion to partial write possible for AAI. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix message printing for SPI RES on spew level.hailfinger2010-06-201-22/+16
| | | | | | | | | | | Use a blacklist instead of a whitelist for 4-byte SPI RDID. Tell users where to report bugs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* So far, we have up to 4 different names for the same thing (ignoringhailfinger2010-05-311-6/+6
| | | | | | | | | | | | | | | | | | | | | | capitalization): CONFIG_FT2232SPI (makefile config option) FT2232_SPI_SUPPORT (#define) ft2232spi (programmer name) ft2232_spi.c (programmer file) Use CONFIG_* with underscores for makefile config options and #defines and kill the useless _SUPPORT idiom. Use lowercase names with underscores for programmer names and programmer files. With this, you can run "grep -i ft2232_spi" and find everything related to the ft2232_spi driver. Same applies to all other programmers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Some chips implement the RES (0xab) opcode, but they use a non-standardhailfinger2010-05-281-6/+32
| | | | | | | | | | | | two byte response instead of the usual one byte response. A two-byte response has the accuracy of REMS and RDID, so don't check for REMS/RDID availability before running a two-byte RES. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Handle the following architectures in generic flashrom code:hailfinger2010-05-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Misha Manulis for testing early versions of this patch on PowerPC (big endian) with the satasii programmer. Thanks to Segher Boessenkool for design review and for helping out with compiler tricks and pointing out that we need eieio on PowerPC. Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). Thanks to Uwe Hermann for compile and runtime testing on x86_64. DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH! This patch only provides the infrastructure, but does not convert any drivers, so flashrom will compile, but it won't do the right thing on non-x86 platforms. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Every SPI programmer driver had its own completely different chip writehailfinger2010-05-211-2/+48
| | | | | | | | | | | | | | | | implementation, and all of them were insufficiently commented. Create spi_write_chunked as a copy of spi_read_chunked and convert all SPI programmers to use it. No functional changes except: - Bus Pirate uses 12 Byte writes instead of 8 Byte writes - SB600 uses 5 Byte writes instead of 1 Byte writes Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert chips' message printing to msg_c*snelson2010-03-241-69/+58
| | | | | | | | | | | Fixed suggestions by Carl-Daniel. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split spi.c into programmer and chip codesnelson2010-02-261-0/+992
Remove chipdriver.h include from flash.h Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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