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authornickysn <nickysn@3ad0048d-3df7-0310-abae-a5850022a9f2>2014-04-04 20:18:47 +0000
committernickysn <nickysn@3ad0048d-3df7-0310-abae-a5850022a9f2>2014-04-04 20:18:47 +0000
commit843f45e9efb65426f080d29c35f8e26b4bbcb09d (patch)
tree2eb434599b45dc3ed5412994fdd8f4e22655f694 /compiler/i8086/cgcpu.pas
parent61b70c85258f747ba782c52decd04a0b41aac13b (diff)
downloadfpc-843f45e9efb65426f080d29c35f8e26b4bbcb09d.tar.gz
* i8086 far data model fixes in the copying of openarray value params
git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@27470 3ad0048d-3df7-0310-abae-a5850022a9f2
Diffstat (limited to 'compiler/i8086/cgcpu.pas')
-rw-r--r--compiler/i8086/cgcpu.pas11
1 files changed, 9 insertions, 2 deletions
diff --git a/compiler/i8086/cgcpu.pas b/compiler/i8086/cgcpu.pas
index b9dc028ca7..69dc3209ff 100644
--- a/compiler/i8086/cgcpu.pas
+++ b/compiler/i8086/cgcpu.pas
@@ -1869,7 +1869,7 @@ unit cgcpu;
{ Allocate SI and load it with source }
getcpuregister(list,NR_SI);
- if (ref.segment=NR_NO) or
+ if ((ref.segment=NR_NO) and (segment_regs_equal(NR_SS,NR_DS) or (ref.base<>NR_BP))) or
(is_segment_reg(ref.segment) and segment_regs_equal(ref.segment,NR_DS)) then
begin
a_loadaddr_ref_reg(list,ref,NR_SI);
@@ -1880,7 +1880,12 @@ unit cgcpu;
hlcg.a_loadaddr_ref_reg(list,voidnearpointertype,voidnearpointertype,ref,NR_SI);
list.concat(taicpu.op_reg(A_PUSH,S_W,NR_DS));
saved_ds:=true;
- list.concat(taicpu.op_reg(A_PUSH,S_W,ref.segment));
+ if ref.segment<>NR_NO then
+ list.concat(taicpu.op_reg(A_PUSH,S_W,ref.segment))
+ else if ref.base=NR_BP then
+ list.concat(taicpu.op_reg(A_PUSH,S_W,NR_SS))
+ else
+ internalerror(2014040403);
list.concat(taicpu.op_reg(A_POP,S_W,NR_DS));
end;
@@ -1928,6 +1933,8 @@ unit cgcpu;
{ patch the new address, but don't use a_load_reg_reg, that will add a move instruction
that can confuse the reg allocator }
list.concat(Taicpu.Op_reg_reg(A_MOV,S_W,NR_SP,destreg));
+ if current_settings.x86memorymodel in x86_far_data_models then
+ list.concat(Taicpu.Op_reg_reg(A_MOV,S_W,NR_SS,GetNextReg(destreg)));
end;