diff options
| author | sergei <sergei@3ad0048d-3df7-0310-abae-a5850022a9f2> | 2014-06-11 22:31:40 +0000 |
|---|---|---|
| committer | sergei <sergei@3ad0048d-3df7-0310-abae-a5850022a9f2> | 2014-06-11 22:31:40 +0000 |
| commit | b3a36d27716f10e0a5dd71599f5e1664d7fd1659 (patch) | |
| tree | e7b6e69bbe97fb475903f71930761e991219664a /compiler/i8086/i8086prop.inc | |
| parent | 11b7995e2abef64d02210dea09315f9d4e46cd6d (diff) | |
| download | fpc-b3a36d27716f10e0a5dd71599f5e1664d7fd1659.tar.gz | |
* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.
git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@27934 3ad0048d-3df7-0310-abae-a5850022a9f2
Diffstat (limited to 'compiler/i8086/i8086prop.inc')
| -rw-r--r-- | compiler/i8086/i8086prop.inc | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/compiler/i8086/i8086prop.inc b/compiler/i8086/i8086prop.inc index ce6c618d3c..6ef7e6d066 100644 --- a/compiler/i8086/i8086prop.inc +++ b/compiler/i8086/i8086prop.inc @@ -161,8 +161,6 @@ (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), -(Ch: (Ch_All, Ch_None, Ch_None)), -(Ch: (Ch_RECX, Ch_None, Ch_None)), (Ch: (Ch_RECX, Ch_None, Ch_None)), (Ch: (Ch_RECX, Ch_None, Ch_None)), (Ch: (Ch_ROp1, Ch_None, Ch_None)), @@ -201,7 +199,6 @@ (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), -(Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_Wop2, Ch_Rop1, Ch_None)), (Ch: (Ch_Wop2, Ch_Rop1, Ch_None)), (Ch: (Ch_RWEAX, Ch_WEDX, Ch_WFlags)), @@ -272,7 +269,6 @@ (Ch: (Ch_RWESP, Ch_WFlags, Ch_None)), (Ch: (Ch_RWESP, Ch_WFlags, Ch_None)), (Ch: (Ch_RWESP, Ch_WFLAGS, Ch_None)), -(Ch: (Ch_RWESP, Ch_WFlags, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), @@ -306,7 +302,6 @@ (Ch: (Ch_RWESP, Ch_RFlags, Ch_None)), (Ch: (Ch_RWESP, Ch_RFlags, Ch_None)), (Ch: (Ch_RWESP, Ch_RFLAGS, Ch_None)), -(Ch: (Ch_RWESP, Ch_RFlags, Ch_None)), (Ch: (Ch_Mop2, Ch_Rop1, Ch_None)), (Ch: (Ch_Mop2, Ch_Rop1, Ch_RWFlags)), (Ch: (Ch_Mop2, Ch_Rop1, Ch_RWFlags)), @@ -335,7 +330,6 @@ (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), -(Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_None, Ch_None, Ch_None)), (Ch: (Ch_None, Ch_None, Ch_None)), (Ch: (Ch_None, Ch_None, Ch_None)), @@ -596,12 +590,6 @@ (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), -(Ch: (Ch_Wop2, Ch_Rop1, Ch_None)), -(Ch: (Ch_Wop2, Ch_Rop1, Ch_None)), -(Ch: (Ch_MRAX, Ch_WRDX, Ch_None)), -(Ch: (Ch_All, Ch_None, Ch_None)), -(Ch: (Ch_All, Ch_None, Ch_None)), -(Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), @@ -682,9 +670,6 @@ (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_All, Ch_None, Ch_None)), -(Ch: (Ch_RRAX, Ch_WMemEDI, Ch_RWRDI)), -(Ch: (Ch_WRAX, Ch_RWRSI, Ch_None)), -(Ch: (Ch_All, Ch_None, Ch_None)), (Ch: (Ch_Wop3, Ch_Rop2, Ch_Rop1)), (Ch: (Ch_Wop3, Ch_Rop2, Ch_Rop1)), (Ch: (Ch_Wop3, Ch_Rop2, Ch_Rop1)), |