Initial version of mipsel-embedded Target for pic32mx chips.

You will need to compile binutils from https://github.com/chipKIT32/chipKIT-cxx/tree/master/src45x/binutils
Startupcode still needs some debugging and there exists a problem with alignment of dwarf debug info, besides this everything pretty much works.


git-svn-id: http://svn.freepascal.org/svn/fpc/branches/mips_embedded@25052 3ad0048d-3df7-0310-abae-a5850022a9f2

6 files changed, 119 insertions, 6 deletions

diff --git a/compiler/mips/cpugas.pas b/compiler/mips/cpugas.pas
index 13b5b09aa2..c4a37f2930 100644
--- a/compiler/mips/cpugas.pas
+++ b/compiler/mips/cpugas.pas
@@ -102,7 +102,8 @@ unit cpugas;
          { ABI selection }
          Replace(result,'$ABI','-mabi='+abitypestr[mips_abi]);
          { ARCH selection }
-         Replace(result,'$ARCH','-march='+lower(cputypestr[current_settings.cputype]));
+         // Replace(result,'$ARCH','-march='+lower(cputypestr[current_settings.cputype])+' '+'-mtune='+lower(cputypestr[current_settings.cputype])); TODO This does not work yet
+         Replace(result,'$ARCH','-march=pic32mx -mtune=pic32mx');
       end;
 
 {****************************************************************************}
@@ -380,7 +381,7 @@ unit cpugas;
         idtxt: 'AS';
         asmbin: 'as';
         asmcmd: '$ABI $ARCH $NOWARN -EL $PIC -o $OBJ $ASM';
-        supported_targets: [system_mipsel_linux];
+        supported_targets: [system_mipsel_linux,system_mipsel_embedded];
         flags: [ af_needar, af_smartlink_sections];
         labelprefix: '.L';
         comment: '# ';
diff --git a/compiler/mips/cpuinfo.pas b/compiler/mips/cpuinfo.pas
index 9444bba291..abdb25650a 100644
--- a/compiler/mips/cpuinfo.pas
+++ b/compiler/mips/cpuinfo.pas
@@ -38,7 +38,8 @@ Type
        cpu_mips4,
        cpu_mips5,
        cpu_mips32,
-       cpu_mips32r2
+       cpu_mips32r2,
+       cpu_pic32mx
       );
 
    tfputype =(fpu_none,fpu_soft,fpu_mips2,fpu_mips3);
@@ -85,7 +86,8 @@ Const
      { cpu_mips4        } 'MIPS4',
      { cpu_mips5        } 'MIPS5',
      { cpu_mips32       } 'MIPS32',
-     { cpu_mips32r2     } 'MIPS32R2'
+     { cpu_mips32r2     } 'MIPS32R2',
+     { cpu_pic32mx      } 'PIC32MX'
    );
 
    fputypestr : array[tfputype] of string[9] = ('',
@@ -105,7 +107,112 @@ Const
       { abi_eabi    } 'eabi'
      );
 
+//{$ifdef MIPSEL}
+//   mips_abi : tabitype = abi_eabi;
+//{$else}
    mips_abi : tabitype = abi_default;
+//{$endif}
+
+{$ifdef MIPSEL}
+type
+   tcpuflags=(CPUMIPS_HAS_XXXX); //Todo: Does this need to be filled?
+
+const
+  cpu_capabilities : array[tcputype] of set of tcpuflags =
+    ( { cpu_none } [],
+      { cpu_mips1 } [],
+      { cpu_mips2 } [],
+      { cpu_mips3 } [],
+      { cpu_mips4 } [],
+      { cpu_mips5 } [],
+      { cpu_mips32 } [],
+      { cpu_mips32r2 } [],
+      { cpu_pic32mx } []
+    );
+
+
+type
+   tcontrollertype =
+     (ct_none,
+      { pic32mx }
+      ct_pic32mx110f016b,
+      ct_pic32mx110f016c,
+      ct_pic32mx110f016d,
+      ct_pic32mx120f032b,
+      ct_pic32mx120f032c,
+      ct_pic32mx120f032d,
+      ct_pic32mx130f064b,
+      ct_pic32mx130f064c,
+      ct_pic32mx130f064d,
+      ct_pic32mx150f128b,
+      ct_pic32mx150f128c,
+      ct_pic32mx150f128d,
+      ct_pic32mx210f016b,
+      ct_pic32mx210f016c,
+      ct_pic32mx210f016d,
+      ct_pic32mx220f032b,
+      ct_pic32mx220f032c,
+      ct_pic32mx220f032d,
+      ct_pic32mx230f064b,
+      ct_pic32mx230f064c,
+      ct_pic32mx230f064d,
+      ct_pic32mx250f128b,
+      ct_pic32mx250f128c,
+      ct_pic32mx250f128d,
+      ct_pic32mx775f256h,
+      ct_pic32mx775f256l,
+      ct_pic32mx775f512h,
+      ct_pic32mx775f512l,
+      ct_pic32mx795f512h,
+      ct_pic32mx795f512l
+     );
+
+    { We know that there are fields after sramsize
+      but we don't care about this warning }
+   {$WARN 3177 OFF}
+const
+   embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
+   (
+      (controllertypestr:'';		controllerunitstr:'';	flashbase:0;	flashsize:0;	srambase:0;	sramsize:0),
+
+      { PIC32MX1xx Series}
+      (controllertypestr:'PIC32MX110F016B';	controllerunitstr:'PIC32MX1xxFxxxB';	flashbase:$9d000000;	flashsize:$00004000;	srambase:$A0000000;	sramsize:$00001000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX110F016C';	controllerunitstr:'PIC32MX1xxFxxxC';	flashbase:$9d000000;	flashsize:$00004000;	srambase:$A0000000;	sramsize:$00001000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX110F016D';	controllerunitstr:'PIC32MX1xxFxxxD';	flashbase:$9d000000;	flashsize:$00004000;	srambase:$A0000000;	sramsize:$00001000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX120F032B';	controllerunitstr:'PIC32MX1xxFxxxB';	flashbase:$9d000000;	flashsize:$00008000;	srambase:$A0000000;	sramsize:$00002000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX120F032C';	controllerunitstr:'PIC32MX1xxFxxxC';	flashbase:$9d000000;	flashsize:$00008000;	srambase:$A0000000;	sramsize:$00002000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX120F032D';	controllerunitstr:'PIC32MX1xxFxxxD';	flashbase:$9d000000;	flashsize:$00008000;	srambase:$A0000000;	sramsize:$00002000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX130F064B';	controllerunitstr:'PIC32MX1xxFxxxB';	flashbase:$9d000000;	flashsize:$00010000;	srambase:$A0000000;	sramsize:$00004000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX130F064C';	controllerunitstr:'PIC32MX1xxFxxxC';	flashbase:$9d000000;	flashsize:$00010000;	srambase:$A0000000;	sramsize:$00004000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX130F064D';	controllerunitstr:'PIC32MX1xxFxxxD';	flashbase:$9d000000;	flashsize:$00010000;	srambase:$A0000000;	sramsize:$00004000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX150F128B';	controllerunitstr:'PIC32MX1xxFxxxB';	flashbase:$9d000000;	flashsize:$00020000;	srambase:$A0000000;	sramsize:$00008000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX150F128C';	controllerunitstr:'PIC32MX1xxFxxxC';	flashbase:$9d000000;	flashsize:$00020000;	srambase:$A0000000;	sramsize:$00008000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX150F128D';	controllerunitstr:'PIC32MX1xxFxxxD';	flashbase:$9d000000;	flashsize:$00020000;	srambase:$A0000000;	sramsize:$00008000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+
+      { PIC32MX2xx Series}
+      (controllertypestr:'PIC32MX210F016B';	controllerunitstr:'PIC32MX2xxFxxxB';	flashbase:$9d000000;	flashsize:$00004000;	srambase:$A0000000;	sramsize:$00001000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX210F016C';	controllerunitstr:'PIC32MX2xxFxxxC';	flashbase:$9d000000;	flashsize:$00004000;	srambase:$A0000000;	sramsize:$00001000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX210F016D';	controllerunitstr:'PIC32MX2xxFxxxD';	flashbase:$9d000000;	flashsize:$00004000;	srambase:$A0000000;	sramsize:$00001000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX220F032B';	controllerunitstr:'PIC32MX2xxFxxxB';	flashbase:$9d000000;	flashsize:$00008000;	srambase:$A0000000;	sramsize:$00002000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX220F032C';	controllerunitstr:'PIC32MX2xxFxxxC';	flashbase:$9d000000;	flashsize:$00008000;	srambase:$A0000000;	sramsize:$00002000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX220F032D';	controllerunitstr:'PIC32MX2xxFxxxD';	flashbase:$9d000000;	flashsize:$00008000;	srambase:$A0000000;	sramsize:$00002000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX230F064B';	controllerunitstr:'PIC32MX2xxFxxxB';	flashbase:$9d000000;	flashsize:$00010000;	srambase:$A0000000;	sramsize:$00004000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX230F064C';	controllerunitstr:'PIC32MX2xxFxxxC';	flashbase:$9d000000;	flashsize:$00010000;	srambase:$A0000000;	sramsize:$00004000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX230F064D';	controllerunitstr:'PIC32MX2xxFxxxD';	flashbase:$9d000000;	flashsize:$00010000;	srambase:$A0000000;	sramsize:$00004000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX250F128B';	controllerunitstr:'PIC32MX2xxFxxxB';	flashbase:$9d000000;	flashsize:$00020000;	srambase:$A0000000;	sramsize:$00008000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX250F128C';	controllerunitstr:'PIC32MX2xxFxxxC';	flashbase:$9d000000;	flashsize:$00020000;	srambase:$80000000;	sramsize:$00008000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+      (controllertypestr:'PIC32MX250F128D';	controllerunitstr:'PIC32MX2xxFxxxD';	flashbase:$9d000000;	flashsize:$00020000;	srambase:$A0000000;	sramsize:$00008000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00000BEF),
+
+      { PIC32MX7x5 Series}
+      (controllertypestr:'PIC32MX775F256H';	controllerunitstr:'PIC32MX7x5FxxxH';	flashbase:$9d000000;	flashsize:$00040000;	srambase:$A0000000;	sramsize:$00010000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00002FEF),
+      (controllertypestr:'PIC32MX775F256L';	controllerunitstr:'PIC32MX7x5FxxxL';	flashbase:$9d000000;	flashsize:$00040000;	srambase:$A0000000;	sramsize:$00010000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00002FEF),
+      (controllertypestr:'PIC32MX775F512H';	controllerunitstr:'PIC32MX7x5FxxxH';	flashbase:$9d000000;	flashsize:$00080000;	srambase:$A0000000;	sramsize:$00010000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00002FEF),
+      (controllertypestr:'PIC32MX775F512L';	controllerunitstr:'PIC32MX7x5FxxxL';	flashbase:$9d000000;	flashsize:$00080000;	srambase:$A0000000;	sramsize:$00010000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00002FEF),
+      (controllertypestr:'PIC32MX795F512H';	controllerunitstr:'PIC32MX7x5FxxxH';	flashbase:$9d000000;	flashsize:$00080000;	srambase:$A0000000;	sramsize:$00020000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00002FEF),
+      (controllertypestr:'PIC32MX795F512L';	controllerunitstr:'PIC32MX7x5FxxxL';	flashbase:$9d000000;	flashsize:$00080000;	srambase:$A0000000;	sramsize:$00020000;  eeprombase:0;   eepromsize:0;    bootbase:$BFC00000;     bootsize:$00002FEF)
+  );
+
+{$endif MIPSEL}
 
    { Supported optimizations, only used for information }
    supported_optimizerswitches = [cs_opt_regvar,cs_opt_loopunroll,cs_opt_nodecse,
diff --git a/compiler/mips/cputarg.pas b/compiler/mips/cputarg.pas
index a7743f040b..6437c4675e 100644
--- a/compiler/mips/cputarg.pas
+++ b/compiler/mips/cputarg.pas
@@ -46,6 +46,9 @@ implementation
     {$ifndef NOTARGETLINUX}
       ,t_linux
     {$endif}
+    {$ifndef NOTARGETEMBEDDED}
+      ,t_embed
+    {$endif}
 
 {**************************************
              Assemblers
diff --git a/compiler/mips/hlcgcpu.pas b/compiler/mips/hlcgcpu.pas
index 7d494d9428..f60a265df8 100644
--- a/compiler/mips/hlcgcpu.pas
+++ b/compiler/mips/hlcgcpu.pas
@@ -93,7 +93,7 @@ implementation
     begin
       cgsubsetsize:=def_cgsize(subsetsize);
       cgtosize:=def_cgsize(tosize);
-      if (current_settings.cputype<>cpu_mips32r2) then
+      if (current_settings.cputype<>cpu_mips32r2) and (current_settings.cputype<>cpu_pic32mx) then
         inherited a_load_subsetreg_reg(list,subsetsize,tosize,sreg,destreg)
       else if (sreg.bitlen>32) then
         InternalError(2013070201)
@@ -121,7 +121,7 @@ implementation
 
   procedure thlcgmips.a_load_regconst_subsetreg_intern(list: TAsmList; fromsize, subsetsize: tdef; fromreg: tregister; const sreg: tsubsetregister; slopt: tsubsetloadopt);
     begin
-      if (current_settings.cputype<>cpu_mips32r2) then
+      if (current_settings.cputype<>cpu_mips32r2)  and (current_settings.cputype<>cpu_pic32mx) then
         inherited a_load_regconst_subsetreg_intern(list,fromsize,subsetsize,fromreg,sreg,slopt)
       else if (sreg.bitlen>32) then
         InternalError(2013070202)
diff --git a/compiler/mips/opcode.inc b/compiler/mips/opcode.inc
index 8c69dd8f88..4b607c5f33 100644
--- a/compiler/mips/opcode.inc
+++ b/compiler/mips/opcode.inc
@@ -188,4 +188,5 @@ A_MFC0,
 A_MTC0,
 A_SDBBP,
 A_WRPGPR,
+A_ERET,
 A_END_DEF
diff --git a/compiler/mips/strinst.inc b/compiler/mips/strinst.inc
index f14ccc7377..d3df8fdb18 100644
--- a/compiler/mips/strinst.inc
+++ b/compiler/mips/strinst.inc
@@ -188,4 +188,5 @@
 'mtc0',
 'sdbbp',
 'wrpgpr',
+'eret',
 'end_def'