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-rw-r--r--compiler/arm/rgcpu.pas14
1 files changed, 14 insertions, 0 deletions
diff --git a/compiler/arm/rgcpu.pas b/compiler/arm/rgcpu.pas
index fdb9e0df9e..ca55f59f2c 100644
--- a/compiler/arm/rgcpu.pas
+++ b/compiler/arm/rgcpu.pas
@@ -290,6 +290,10 @@ unit rgcpu;
if abs(spilltemp.offset)>4095 then
exit;
+ { ldr can't set the flags }
+ if instr.oppostfix=PF_S then
+ exit;
+
if GenerateThumbCode and
(abs(spilltemp.offset)>1020) then
exit;
@@ -304,6 +308,11 @@ unit rgcpu;
(get_alias(getsupreg(oper[0]^.reg))=orgreg) and
(get_alias(getsupreg(oper[1]^.reg))<>orgreg) then
begin
+ { do not replace if we're on Thumb, ldr/str cannot be used with rX>r7 }
+ if GenerateThumbCode and
+ (getsupreg(oper[1]^.reg)>RS_R7) then
+ exit;
+
{ str expects the register in oper[0] }
instr.loadreg(0,oper[1]^.reg);
instr.loadref(1,spilltemp);
@@ -314,6 +323,11 @@ unit rgcpu;
(get_alias(getsupreg(oper[1]^.reg))=orgreg) and
(get_alias(getsupreg(oper[0]^.reg))<>orgreg) then
begin
+ { do not replace if we're on Thumb, ldr/str cannot be used with rX>r7 }
+ if GenerateThumbCode and
+ (getsupreg(oper[0]^.reg)>RS_R7) then
+ exit;
+
instr.loadref(1,spilltemp);
opcode:=A_LDR;
result:=true;