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-rw-r--r--compiler/arm/aasmcpu.pas171
-rw-r--r--compiler/arm/agarmgas.pas2
-rw-r--r--compiler/arm/aoptcpu.pas30
-rw-r--r--compiler/arm/aoptcpub.pas24
-rw-r--r--compiler/arm/cgcpu.pas57
-rw-r--r--compiler/arm/cpubase.pas2
-rw-r--r--compiler/arm/cpuelf.pas2
-rw-r--r--compiler/arm/cpupara.pas2
-rw-r--r--compiler/arm/cpupi.pas6
-rw-r--r--compiler/arm/narmadd.pas6
-rw-r--r--compiler/arm/narmcnv.pas3
-rw-r--r--compiler/arm/raarmgas.pas6
-rw-r--r--compiler/arm/rgcpu.pas8
13 files changed, 252 insertions, 67 deletions
diff --git a/compiler/arm/aasmcpu.pas b/compiler/arm/aasmcpu.pas
index 81c10250cc..fe53b1a12e 100644
--- a/compiler/arm/aasmcpu.pas
+++ b/compiler/arm/aasmcpu.pas
@@ -381,6 +381,8 @@ implementation
if assigned(add_reg_instruction_hook) and (i in regset^) then
add_reg_instruction_hook(self,newreg(R_MMREGISTER,i,regsetsubregtype));
end;
+ else
+ internalerror(2019050932);
end;
end;
end;
@@ -1141,6 +1143,8 @@ implementation
begin
inc(extradataoffset,multiplier*(((tai_realconst(hp).savesize-4)+3) div 4));
end;
+ else
+ ;
end;
{ check if the same constant has been already inserted into the currently handled list,
if yes, reuse it }
@@ -1200,6 +1204,8 @@ implementation
begin
inc(curinspos,multiplier*((tai_realconst(hp).savesize+3) div 4));
end;
+ else
+ ;
end;
{ special case for case jump tables }
penalty:=0;
@@ -1270,6 +1276,8 @@ implementation
or if we splitted them so split before }
CheckLimit(hp,4);
end;
+ else
+ ;
end;
end;
@@ -1424,8 +1432,11 @@ implementation
end;
end;
end;
+ else;
end;
end;
+ else
+ ;
end;
curtai:=tai(curtai.Next);
@@ -1489,8 +1500,12 @@ implementation
taicpu(curtai).ops:=2;
end;
end;
+ else
+ ;
end;
end;
+ else
+ ;
end;
curtai:=tai(curtai.Next);
@@ -1536,55 +1551,59 @@ implementation
begin
case curtai.typ of
ait_instruction:
- if IsIT(taicpu(curtai).opcode) then
- begin
- levels := GetITLevels(taicpu(curtai).opcode);
- if levels < 4 then
- begin
- i:=levels;
- hp1:=tai(curtai.Next);
- while assigned(hp1) and
- (i > 0) do
- begin
- if hp1.typ=ait_instruction then
- begin
- dec(i);
- if (i = 0) and
- mustbelast(hp1) then
- begin
- hp1:=nil;
- break;
- end;
- end;
- hp1:=tai(hp1.Next);
- end;
+ begin
+ if IsIT(taicpu(curtai).opcode) then
+ begin
+ levels := GetITLevels(taicpu(curtai).opcode);
+ if levels < 4 then
+ begin
+ i:=levels;
+ hp1:=tai(curtai.Next);
+ while assigned(hp1) and
+ (i > 0) do
+ begin
+ if hp1.typ=ait_instruction then
+ begin
+ dec(i);
+ if (i = 0) and
+ mustbelast(hp1) then
+ begin
+ hp1:=nil;
+ break;
+ end;
+ end;
+ hp1:=tai(hp1.Next);
+ end;
- if assigned(hp1) then
- begin
- // We are pointing at the first instruction after the IT block
- while assigned(hp1) and
- (hp1.typ<>ait_instruction) do
- hp1:=tai(hp1.Next);
-
- if assigned(hp1) and
- (hp1.typ=ait_instruction) and
- IsIT(taicpu(hp1).opcode) then
- begin
- if (levels+GetITLevels(taicpu(hp1).opcode) <= 4) and
- ((taicpu(curtai).oper[0]^.cc=taicpu(hp1).oper[0]^.cc) or
- (taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc))) then
- begin
- taicpu(curtai).opcode:=getMergedInstruction(taicpu(curtai).opcode,
- taicpu(hp1).opcode,
- taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc));
+ if assigned(hp1) then
+ begin
+ // We are pointing at the first instruction after the IT block
+ while assigned(hp1) and
+ (hp1.typ<>ait_instruction) do
+ hp1:=tai(hp1.Next);
+
+ if assigned(hp1) and
+ (hp1.typ=ait_instruction) and
+ IsIT(taicpu(hp1).opcode) then
+ begin
+ if (levels+GetITLevels(taicpu(hp1).opcode) <= 4) and
+ ((taicpu(curtai).oper[0]^.cc=taicpu(hp1).oper[0]^.cc) or
+ (taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc))) then
+ begin
+ taicpu(curtai).opcode:=getMergedInstruction(taicpu(curtai).opcode,
+ taicpu(hp1).opcode,
+ taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc));
- list.Remove(hp1);
- hp1.Free;
- end;
- end;
- end;
- end;
- end;
+ list.Remove(hp1);
+ hp1.Free;
+ end;
+ end;
+ end;
+ end;
+ end;
+ end
+ else
+ ;
end;
curtai:=tai(curtai.Next);
@@ -1611,6 +1630,8 @@ implementation
case taicpu(curtai).opcode of
A_AND: taicpu(curtai).opcode:=A_BIC;
A_BIC: taicpu(curtai).opcode:=A_AND;
+ else
+ internalerror(2019050931);
end;
taicpu(curtai).oper[2]^.val:=(not taicpu(curtai).oper[2]^.val) and $FFFFFFFF;
end
@@ -1623,10 +1644,14 @@ implementation
case taicpu(curtai).opcode of
A_ADD: taicpu(curtai).opcode:=A_SUB;
A_SUB: taicpu(curtai).opcode:=A_ADD;
+ else
+ internalerror(2019050930);
end;
taicpu(curtai).oper[2]^.val:=-taicpu(curtai).oper[2]^.val;
end;
end;
+ else
+ ;
end;
curtai:=tai(curtai.Next);
@@ -1674,6 +1699,8 @@ implementation
end;
end;
end;
+ else
+ ;
end;
curtai:=tai(curtai.Next);
@@ -1699,6 +1726,7 @@ implementation
(taicpu(curtai).oper[2]^.typ=top_shifterop) then
begin
case taicpu(curtai).oper[2]^.shifterop^.shiftmode of
+ SM_NONE: ;
SM_LSL: taicpu(curtai).opcode:=A_LSL;
SM_LSR: taicpu(curtai).opcode:=A_LSR;
SM_ASR: taicpu(curtai).opcode:=A_ASR;
@@ -1735,8 +1763,12 @@ implementation
begin
taicpu(curtai).opcode:=A_SVC;
end;
+ else
+ ;
end;
end;
+ else
+ ;
end;
curtai:=tai(curtai.Next);
@@ -2971,6 +3003,7 @@ implementation
shift:=0;
typ:=0;
case oper[op]^.shifterop^.shiftmode of
+ SM_None: ;
SM_LSL: begin typ:=0; shift:=oper[op]^.shifterop^.shiftimm; end;
SM_LSR: begin typ:=1; shift:=oper[op]^.shifterop^.shiftimm; if shift=32 then shift:=0; end;
SM_ASR: begin typ:=2; shift:=oper[op]^.shifterop^.shiftimm; if shift=32 then shift:=0; end;
@@ -3983,6 +4016,8 @@ implementation
bytes:=bytes or ((Rd and $F) shl 12);
bytes:=bytes or (((Rd and $10) shr 4) shl 22);
end;
+ else
+ Message(asmw_e_invalid_opcode_and_operands);
end;
end;
#$41,#$91: // VMRS/VMSR
@@ -4143,6 +4178,8 @@ implementation
d:=(rd shr 4) and 1;
rd:=rd and $F;
end;
+ else
+ internalerror(2019050929);
end;
m:=0;
@@ -4163,6 +4200,8 @@ implementation
m:=(rm shr 4) and 1;
rm:=rm and $F;
end;
+ else
+ internalerror(2019050928);
end;
bytes:=bytes or (Rd shl 12);
@@ -4179,6 +4218,8 @@ implementation
PF_F64S32,
PF_F64U32:
bytes:=bytes or (1 shl 8);
+ else
+ ;
end;
if oppostfix in [PF_S32F32,PF_S32F64,PF_U32F32,PF_U32F64] then
@@ -4187,6 +4228,8 @@ implementation
PF_S32F64,
PF_S32F32:
bytes:=bytes or (1 shl 16);
+ else
+ ;
end;
bytes:=bytes or (1 shl 18);
@@ -4257,9 +4300,9 @@ implementation
rn:=16;
end;
- else
- Rn:=0;
- message(asmw_e_invalid_opcode_and_operands);
+ else
+ Rn:=0;
+ message(asmw_e_invalid_opcode_and_operands);
end;
case oppostfix of
@@ -4271,10 +4314,10 @@ implementation
bytes:=bytes or (1 shl 8);
D:=(rd shr 4) and $1; Rd:=Rd and $F;
end;
- else
- begin
- D:=rd and $1; Rd:=Rd shr 1;
- end;
+ else
+ begin
+ D:=rd and $1; Rd:=Rd shr 1;
+ end;
end;
case oppostfix of
@@ -4283,6 +4326,8 @@ implementation
PF_F64U16,PF_F32U16,
PF_F32U32,PF_F64U32:
bytes:=bytes or (1 shl 16);
+ else
+ ;
end;
if oppostfix in [PF_S32F32,PF_S32F64,PF_U32F32,PF_U32F64,PF_S16F32,PF_S16F64,PF_U16F32,PF_U16F64] then
@@ -4335,6 +4380,8 @@ implementation
bytes:=bytes or (1 shl 23);
PF_DB,PF_DBS,PF_DBD,PF_DBX:
bytes:=bytes or (2 shl 23);
+ else
+ ;
end;
case oppostfix of
@@ -4343,6 +4390,8 @@ implementation
bytes:=bytes or (1 shl 8);
bytes:=bytes or (1 shl 0); // Offset is odd
end;
+ else
+ ;
end;
dp_operation:=(oper[1]^.subreg=R_SUBFD);
@@ -4634,6 +4683,8 @@ implementation
bytes:=bytes or ((oper[2]^.val shr 2) and $7F);
end;
end;
+ else
+ internalerror(2019050926);
end;
end;
#$65: { Thumb load/store }
@@ -4770,6 +4821,8 @@ implementation
else
bytes:=bytes or (getsupreg(oper[0]^.reg) shl 8);
end;
+ else
+ internalerror(2019050925);
end;
end;
#$6A: { Thumb: IT }
@@ -5375,6 +5428,8 @@ implementation
case oppostfix of
PF_None,PF_IA,PF_FD: bytes:=bytes or ($1 shl 23);
PF_DB,PF_EA: bytes:=bytes or ($2 shl 23);
+ else
+ message1(asmw_e_invalid_opcode_and_operands, '"Invalid Postfix"');
end;
end;
#$8D: { Thumb-2: BL/BLX }
@@ -5525,6 +5580,9 @@ implementation
PF_D: bytes:=bytes or (0 shl 22) or (1 shl 15);
PF_E: bytes:=bytes or (1 shl 22) or (0 shl 15);
PF_P: bytes:=bytes or (1 shl 22) or (1 shl 15);
+ PF_EP: ;
+ else
+ message1(asmw_e_invalid_opcode_and_operands, '"Invalid postfix"');
end;
end
else
@@ -5599,6 +5657,7 @@ implementation
end;
case roundingmode of
+ RM_NONE: ;
RM_P: bytes:=bytes or (1 shl 5);
RM_M: bytes:=bytes or (2 shl 5);
RM_Z: bytes:=bytes or (3 shl 5);
@@ -5626,6 +5685,7 @@ implementation
bytes:=bytes or (getsupreg(oper[1]^.reg) shl 12);
case roundingmode of
+ RM_NONE: ;
RM_P: bytes:=bytes or (1 shl 5);
RM_M: bytes:=bytes or (2 shl 5);
RM_Z: bytes:=bytes or (3 shl 5);
@@ -5645,6 +5705,7 @@ implementation
bytes:=bytes or (getsupreg(oper[1]^.reg) shl 0);
case roundingmode of
+ RM_NONE: ;
RM_P: bytes:=bytes or (1 shl 5);
RM_M: bytes:=bytes or (2 shl 5);
RM_Z: bytes:=bytes or (3 shl 5);
@@ -5674,6 +5735,8 @@ implementation
Message(asmw_e_invalid_opcode_and_operands);
end;
end;
+ else
+ Message1(asmw_e_invalid_opcode_and_operands, '"Unsupported opcode"');
end;
end;
#$fe: // No written data
diff --git a/compiler/arm/agarmgas.pas b/compiler/arm/agarmgas.pas
index 7668cb4090..7547bd6bd5 100644
--- a/compiler/arm/agarmgas.pas
+++ b/compiler/arm/agarmgas.pas
@@ -218,6 +218,8 @@ unit agarmgas;
s:=s+']';
AM_PREINDEXED:
s:=s+']!';
+ else
+ ;
end;
end;
diff --git a/compiler/arm/aoptcpu.pas b/compiler/arm/aoptcpu.pas
index 65891e4730..6cee67c7a9 100644
--- a/compiler/arm/aoptcpu.pas
+++ b/compiler/arm/aoptcpu.pas
@@ -241,6 +241,8 @@ Implementation
instructionLoadsFromReg :=
(p.oper[I]^.ref^.base = reg) or
(p.oper[I]^.ref^.index = reg);
+ else
+ ;
end;
if instructionLoadsFromReg then exit; {Bailout if we found something}
Inc(I);
@@ -300,6 +302,8 @@ Implementation
A_POP:
Result := (getsupreg(reg) in p.oper[0]^.regset^) or
(reg=NR_STACK_POINTER_REG);
+ else
+ ;
end;
if Result then
@@ -316,6 +320,8 @@ Implementation
Result :=
(taicpu(p).oper[0]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) and
(taicpu(p).oper[0]^.ref^.base = reg);
+ else
+ ;
end;
end;
@@ -2252,8 +2258,12 @@ Implementation
RemoveSuperfluousVMov(p, hp1, 'VOpVMov2VOp') then
Result:=true;
end
+ else
+ ;
end;
end;
+ else
+ ;
end;
end;
@@ -2431,8 +2441,12 @@ Implementation
end;
end;
end;
+ else
+ ;
end;
end;
+ else
+ ;
end;
p := tai(p.next)
end;
@@ -2512,6 +2526,8 @@ Implementation
for r:=RS_R0 to RS_R15 do
if r in p.oper[i]^.regset^ then
CheckLiveStart(newreg(R_INTREGISTER,r,R_SUBWHOLE));
+ else
+ ;
end;
{ if live of any reg used by hp1 ends at hp1 and p uses this register then
@@ -2531,6 +2547,8 @@ Implementation
for r:=RS_R0 to RS_R15 do
if r in hp1.oper[i]^.regset^ then
CheckLiveEnd(newreg(R_INTREGISTER,r,R_SUBWHOLE));
+ else
+ ;
end;
end;
@@ -2727,7 +2745,11 @@ Implementation
A_ITETT:
if l=4 then taicpu(hp).opcode := A_ITET;
A_ITTTT:
- if l=4 then taicpu(hp).opcode := A_ITTT;
+ begin
+ if l=4 then taicpu(hp).opcode := A_ITTT;
+ end
+ else
+ ;
end;
break;
@@ -2958,8 +2980,12 @@ Implementation
end;
end;
end;
+ else
+ ;
end;
end;
+ else
+ ;
end;
p := tai(p.next)
end;
@@ -3110,6 +3136,8 @@ Implementation
SM_LSR: taicpu(p).opcode:=A_LSR;
SM_ASR: taicpu(p).opcode:=A_ASR;
SM_ROR: taicpu(p).opcode:=A_ROR;
+ else
+ internalerror(2019050912);
end;
if taicpu(p).oper[2]^.shifterop^.rs<>NR_NO then
diff --git a/compiler/arm/aoptcpub.pas b/compiler/arm/aoptcpub.pas
index 25d2f50bd2..bc4a39e218 100644
--- a/compiler/arm/aoptcpub.pas
+++ b/compiler/arm/aoptcpub.pas
@@ -121,12 +121,16 @@ Implementation
result:=false;
case taicpu(p1).opcode of
A_LDR:
- { special handling for LDRD }
- if (taicpu(p1).oppostfix=PF_D) and (getsupreg(taicpu(p1).oper[0]^.reg)+1=getsupreg(Reg)) then
- begin
- result:=true;
- exit;
- end;
+ begin
+ { special handling for LDRD }
+ if (taicpu(p1).oppostfix=PF_D) and (getsupreg(taicpu(p1).oper[0]^.reg)+1=getsupreg(Reg)) then
+ begin
+ result:=true;
+ exit;
+ end;
+ end;
+ else
+ ;
end;
for i:=0 to taicpu(p1).ops-1 do
case taicpu(p1).oper[i]^.typ of
@@ -134,8 +138,12 @@ Implementation
if (taicpu(p1).oper[i]^.reg=Reg) and (taicpu(p1).spilling_get_operation_type(i) in [operand_write,operand_readwrite]) then
exit(true);
top_ref:
- if (taicpu(p1).spilling_get_operation_type_ref(i,Reg)<>operand_read) then
- exit(true);
+ begin
+ if (taicpu(p1).spilling_get_operation_type_ref(i,Reg)<>operand_read) then
+ exit(true);
+ end
+ else
+ ;
end;
end;
diff --git a/compiler/arm/cgcpu.pas b/compiler/arm/cgcpu.pas
index 51ac562770..7478e4b70e 100644
--- a/compiler/arm/cgcpu.pas
+++ b/compiler/arm/cgcpu.pas
@@ -898,9 +898,11 @@ unit cgcpu;
a_load_const_reg(list, size, a, dst);
exit;
end;
+ else
+ ;
end;
ovloc.loc:=LOC_VOID;
- if {$ifopt R+}(a<>-2147483648) and{$endif} not setflags and is_shifter_const(-a,shift) then
+ if (a<>-2147483648) and not setflags and is_shifter_const(-a,shift) then
case op of
OP_ADD:
begin
@@ -912,6 +914,8 @@ unit cgcpu;
op:=OP_ADD;
a:=aint(dword(-a));
end
+ else
+ ;
end;
if is_shifter_const(a,shift) and not(op in [OP_IMUL,OP_MUL]) then
@@ -960,6 +964,8 @@ unit cgcpu;
ovloc.resflags:=F_CS;
OP_SUB:
ovloc.resflags:=F_CC;
+ else
+ internalerror(2019050922);
end;
end;
end
@@ -1871,6 +1877,10 @@ unit cgcpu;
firstfloatreg:=RS_NO;
mmregs:=[];
case current_settings.fputype of
+ fpu_none,
+ fpu_soft,
+ fpu_libgcc:
+ ;
fpu_fpa,
fpu_fpa10,
fpu_fpa11:
@@ -1896,6 +1906,8 @@ unit cgcpu;
as the even ones by with a different subtype as it is done on x86 with al/ah }
mmregs:=(rg[R_MMREGISTER].used_in_proc-paramanager.get_volatile_registers_mm(pocall_stdcall))*[0..31];
end;
+ else
+ internalerror(2019050924);
end;
a_reg_alloc(list,NR_STACK_POINTER_REG);
if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
@@ -2080,6 +2092,8 @@ unit cgcpu;
if mmregs<>[] then
list.concat(taicpu.op_ref_regset(A_VSTM,ref,R_MMREGISTER,R_SUBFD,mmregs));
end;
+ else
+ internalerror(2019050923);
end;
end;
end;
@@ -2109,6 +2123,10 @@ unit cgcpu;
mmregs:=[];
saveregs:=[];
case current_settings.fputype of
+ fpu_none,
+ fpu_soft,
+ fpu_libgcc:
+ ;
fpu_fpa,
fpu_fpa10,
fpu_fpa11:
@@ -2138,6 +2156,8 @@ unit cgcpu;
as the even ones by with a different subtype as it is done on x86 with al/ah }
mmregs:=(rg[R_MMREGISTER].used_in_proc-paramanager.get_volatile_registers_mm(pocall_stdcall))*[0..31];
end;
+ else
+ internalerror(2019050926);
end;
if (firstfloatreg<>RS_NO) or
@@ -2186,6 +2206,8 @@ unit cgcpu;
if mmregs<>[] then
list.concat(taicpu.op_ref_regset(A_VLDM,ref,R_MMREGISTER,R_SUBFD,mmregs));
end;
+ else
+ internalerror(2019050921);
end;
end;
@@ -3044,6 +3066,8 @@ unit cgcpu;
case instr.opcode of
A_VMOV:
add_move_instruction(instr);
+ else
+ ;
end;
end;
@@ -3073,6 +3097,10 @@ unit cgcpu;
if (fromsize<>tosize) then
internalerror(2009112901);
end;
+ OS_F32,OS_F64:
+ ;
+ else
+ internalerror(2019050920);
end;
if (fromsize<>tosize) then
@@ -3134,6 +3162,10 @@ unit cgcpu;
if (fromsize<>tosize) then
internalerror(2009112901);
end;
+ OS_F32,OS_F64:
+ ;
+ else
+ internalerror(2019050919);
end;
if (fromsize<>tosize) then
@@ -3347,6 +3379,8 @@ unit cgcpu;
OP_NEG,
OP_NOT :
internalerror(2012022501);
+ else
+ ;
end;
if (setflags or tbasecgarm(cg).cgsetflags) and (op in [OP_ADD,OP_SUB]) then
begin
@@ -3411,6 +3445,8 @@ unit cgcpu;
ovloc.resflags:=F_CS;
OP_SUB:
ovloc.resflags:=F_CC;
+ else
+ internalerror(2019050918);
end;
end;
end
@@ -3484,6 +3520,8 @@ unit cgcpu;
OP_NEG,
OP_NOT :
internalerror(2012022502);
+ else
+ ;
end;
if (setflags or tbasecgarm(cg).cgsetflags) and (op in [OP_ADD,OP_SUB]) then
begin
@@ -3512,6 +3550,8 @@ unit cgcpu;
ovloc.resflags:=F_CS;
OP_SUB:
ovloc.resflags:=F_CC;
+ else
+ internalerror(2019050917);
end;
end;
end
@@ -4087,6 +4127,8 @@ unit cgcpu;
op:=OP_ADD;
a:=aint(dword(-a));
end
+ else
+ ;
end;
if is_thumb_imm(a) and (op in [OP_ADD,OP_SUB]) then
@@ -4106,6 +4148,8 @@ unit cgcpu;
OP_SUB:
//!!! ovloc.resflags:=F_CC;
;
+ else
+ ;
end;
end;
end
@@ -4435,6 +4479,11 @@ unit cgcpu;
OS_S8: list.concat(taicpu.op_reg_reg(A_SXTB,dst,dst));
OS_16: list.concat(taicpu.op_reg_reg(A_UXTH,dst,dst));
OS_S16: list.concat(taicpu.op_reg_reg(A_SXTH,dst,dst));
+ OS_32,
+ OS_S32:
+ ;
+ else
+ internalerror(2019050916);
end;
end
else
@@ -4450,7 +4499,7 @@ unit cgcpu;
l1 : longint;
begin
ovloc.loc:=LOC_VOID;
- if {$ifopt R+}(a<>-2147483648) and{$endif} is_shifter_const(-a,shift) then
+ if (a<>-2147483648) and is_shifter_const(-a,shift) then
case op of
OP_ADD:
begin
@@ -4462,6 +4511,8 @@ unit cgcpu;
op:=OP_ADD;
a:=aint(dword(-a));
end
+ else
+ ;
end;
if is_shifter_const(a,shift) and not(op in [OP_IMUL,OP_MUL]) then
@@ -4566,6 +4617,8 @@ unit cgcpu;
ovloc.resflags:=F_CS;
OP_SUB:
ovloc.resflags:=F_CC;
+ else
+ ;
end;
end;
end
diff --git a/compiler/arm/cpubase.pas b/compiler/arm/cpubase.pas
index 3d1719ff1a..d68c7cae1c 100644
--- a/compiler/arm/cpubase.pas
+++ b/compiler/arm/cpubase.pas
@@ -780,6 +780,8 @@ unit cpubase;
((((doublerec.bytes[6] and $7f)=$40) and ((doublerec.bytes[7] and $c0)=0)) or
(((doublerec.bytes[6] and $7f)=$3f) and ((doublerec.bytes[7] and $c0)=$c0)));
end;
+ else
+ ;
end;
end;
diff --git a/compiler/arm/cpuelf.pas b/compiler/arm/cpuelf.pas
index 4930a113eb..eef6103769 100644
--- a/compiler/arm/cpuelf.pas
+++ b/compiler/arm/cpuelf.pas
@@ -588,6 +588,8 @@ implementation
data.Write(zero,4);
continue;
end;
+ else
+ ;
end;
if (objreloc.flags and rf_raw)=0 then
diff --git a/compiler/arm/cpupara.pas b/compiler/arm/cpupara.pas
index 9dae34e7a2..b2655e12a0 100644
--- a/compiler/arm/cpupara.pas
+++ b/compiler/arm/cpupara.pas
@@ -232,6 +232,8 @@ unit cpupara;
result:=not is_smallset(def);
stringdef :
result:=tstringdef(def).stringtype in [st_shortstring,st_longstring];
+ else
+ ;
end;
end;
diff --git a/compiler/arm/cpupi.pas b/compiler/arm/cpupi.pas
index a786d67eba..c232d18954 100644
--- a/compiler/arm/cpupi.pas
+++ b/compiler/arm/cpupi.pas
@@ -57,7 +57,7 @@ unit cpupi;
implementation
uses
- globals,systems,
+ globals,systems,verbose,
cpubase,
tgobj,
symconst,symtype,symsym,symcpu,paramgr,
@@ -156,6 +156,10 @@ unit cpupi;
maxpushedparasize:=align(maxpushedparasize,max(current_settings.alignment.localalignmin,4));
floatsavesize:=0;
case current_settings.fputype of
+ fpu_none,
+ fpu_soft,
+ fpu_libgcc:
+ ;
fpu_fpa,
fpu_fpa10,
fpu_fpa11:
diff --git a/compiler/arm/narmadd.pas b/compiler/arm/narmadd.pas
index 4594ef14af..dc3fb9c276 100644
--- a/compiler/arm/narmadd.pas
+++ b/compiler/arm/narmadd.pas
@@ -344,7 +344,7 @@ interface
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg(A_VMRS, NR_APSR_nzcv, NR_FPSCR));
end;
- fpu_soft:
+ else
{ this case should be handled already by pass1 }
internalerror(2009112404);
end;
@@ -517,6 +517,8 @@ interface
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
nodetype:=oldnodetype;
end;
+ else
+ ;
end;
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo));
@@ -647,6 +649,8 @@ interface
if notnode then
result:=cnotnode.create(result);
end;
+ else
+ internalerror(2019050933);
end;
end
else
diff --git a/compiler/arm/narmcnv.pas b/compiler/arm/narmcnv.pas
index 8af7553b07..3779729174 100644
--- a/compiler/arm/narmcnv.pas
+++ b/compiler/arm/narmcnv.pas
@@ -278,6 +278,9 @@ implementation
else
current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VCVT,location.register,left.location.register), PF_F32U32));
end;
+ else
+ { should be handled in pass 1 }
+ internalerror(2019050934);
end;
end;
diff --git a/compiler/arm/raarmgas.pas b/compiler/arm/raarmgas.pas
index 4eb7b29493..7b73c6d8bb 100644
--- a/compiler/arm/raarmgas.pas
+++ b/compiler/arm/raarmgas.pas
@@ -724,6 +724,8 @@ Unit raarmgas;
end;
end;
end;
+ else
+ ;
end;
end;
@@ -817,6 +819,8 @@ Unit raarmgas;
oper.opr.ref.base:=NR_PC;
oper.opr.ref.symbol:=GetConstLabel(sym,val);
end;
+ else
+ ;
end;
end;
@@ -1143,6 +1147,8 @@ Unit raarmgas;
else
Message(asmr_e_invalid_operand_type); // Otherwise it would have been seen as a AS_REGISTER
end;
+ else
+ Message(asmr_e_invalid_operand_type);
end;
end;
diff --git a/compiler/arm/rgcpu.pas b/compiler/arm/rgcpu.pas
index 4802c67698..8f0279a18b 100644
--- a/compiler/arm/rgcpu.pas
+++ b/compiler/arm/rgcpu.pas
@@ -166,6 +166,8 @@ unit rgcpu;
if current_procinfo.framepointer<>r then
add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(r));
end;
+ else
+ ;
end;
end;
end;
@@ -353,6 +355,8 @@ unit rgcpu;
RS_S21,RS_S23,RS_S25,RS_S27,RS_S29,RS_S31] do
add_edge(supreg,i);
end;
+ else
+ ;
end;
end;
@@ -606,6 +610,8 @@ unit rgcpu;
if current_procinfo.framepointer<>r then
add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(r));
end;
+ else
+ ;
end;
end;
end;
@@ -658,6 +664,8 @@ unit rgcpu;
add_edge(getsupreg(taicpu(p).oper[0]^.reg),i);
end;
end;
+ else
+ ;
end;
end;
end;
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