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* + generate initial cfi for aarch64florian2021-02-171-1/+1
* + Add new LastCommonAsmOp constant to arm and aarch64 CPU targets.pierre2020-10-191-3/+7
* * AArch64: added SIMD instructions (only plain ARMv8-A for now)jonas2020-10-151-4/+22
* * factored out TARMAsmOptimizer.OptPass1UXTBflorian2020-04-151-0/+2
* * patch by J. Gareth Moreton, issue #36271, part 3: support for the other a...florian2019-11-101-0/+23
* + AArch64: FoldShiftProcess optimizationflorian2019-09-051-1/+1
* somehow committing went wrong, second part of last commit:florian2019-09-031-4/+32
* * synchronised with trunk till r40575jonas2018-12-161-0/+3
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| * * support OS_32/OS_64 in AArch64 cgsize2subreg() for MM registers (can happenjonas2018-12-161-0/+3
* | + fpc_eh_return_data_regno() intrinsic to get the return register numbersjonas2018-10-281-0/+10
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* + implement assembler optimization Str/LdrAdd/Sub2Str/Ldr Postindex doneflorian2018-10-231-0/+2
* Fix for bug report #34380pierre2018-10-181-0/+5
* * replaced the saved_XXX_registers arrays with virtual methods insidenickysn2018-04-191-19/+0
* * recognise tb(n)z as branch opcode (patch by Edmund Grimley Evans)jonas2015-05-141-1/+1
* * fixed flags_to_cond() and inverse_cond() for C_GEjonas2015-02-231-2/+2
* * fixed std_param_alignjonas2015-02-231-2/+3
* * added BL and CB(N)Z to is_calljmp()jonas2015-02-231-1/+1
* * fixed cgsize2subreg and cgsize2subreg for mm subreg sizesjonas2015-02-231-5/+6
* - removed ARM leftover tspecialregflag typejonas2015-02-231-3/+0
* + C_CS/C_CC condition and F_HS/F_LO flag aliasesjonas2015-02-231-0/+7
* + IP0/IP1 register aliasesjonas2015-02-231-0/+6
* + shiftedregmodes and extendedregmodes set constantsjonas2015-02-231-0/+4
* * fixed lowercase entry in uppercond2strjonas2015-02-231-1/+1
* * simplified flag_2_cond array rangejonas2015-02-231-1/+1
* + FP/LR register aliasesjonas2015-02-231-0/+10
* + is_shifter_const() function to determine whether a constant can be encodedjonas2015-02-231-0/+111
* * fixed cgsize2subreg() for integer registers (we can use 32 and 64 bitjonas2015-02-231-4/+4
* + added remaining aarch64 shift/extension modesjonas2015-02-231-1/+12
* + tcgsizep2size[] to convert a tcgsize to its power-of-2 bytesizejonas2015-02-231-0/+7
* + SW postfix for sign extending a 32 bit integerjonas2015-02-231-3/+3
* * there is no ROR shiftmode on AArch64jonas2015-02-231-1/+1
* * enable cgsize2subreg() and cgsize2subreg() to differentiate between 32 andjonas2015-02-231-2/+18
* - removed some ARM leftoversjonas2015-02-231-10/+3
* * added SW suffixjonas2015-02-231-3/+3
* * made (X|W)ZR and (W)SP separate registers, because a number ofjonas2015-02-231-5/+3
* * X29 is callee-savedjonas2015-02-231-1/+1
* Implement support for saving and restoring address registers.svenbarth2013-10-051-1/+2
* * adapt conditionflorian2012-11-011-11/+19
* + first cpubase implementation for aarch64florian2012-11-011-0/+450
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