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* + added the Z80 individual flag bits as subregistersnickysn2020-05-111-1/+1
| | | | git-svn-id: https://svn.freepascal.org/svn/fpc/trunk@45342 3ad0048d-3df7-0310-abae-a5850022a9f2
* somehow committing went wrong, second part of last commit:florian2019-09-031-2/+2
| | | | | | | | | | + AArch64: support for vX.8b/vX.16b register names + support for more than 256 registers in the register dat files - removed totherregisterset + AArch64: use vmov to load immediates if possible + AArch64: use eor to clear mm registers git-svn-id: https://svn.freepascal.org/svn/fpc/trunk@42917 3ad0048d-3df7-0310-abae-a5850022a9f2
* + added individual bits of the x86 flags register as subregistersnickysn2017-04-261-1/+1
| | | | git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@35955 3ad0048d-3df7-0310-abae-a5850022a9f2
* Use TRegNameTable instead of array[tregisterindex] of string[10]masta2012-10-221-1/+1
| | | | | | | | | | TRegNameTable is defined in compiler/rgbase.pas and is an array of strings, limited to the maximum length of the used register names. r22792 added a long register name but did not scale the string-size enough, resulting in the compiler built breaking for arm. git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22817 3ad0048d-3df7-0310-abae-a5850022a9f2
* o merge of the branch laksen/arm-embedded of Jeppe Johansen:florian2012-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes a couple of arm-embedded stuff, adds some controllers, start of fpv4_s16 support, for a complete list of changes see below: ------------------------------------------------------------------------ r22787 | laksen | 2012-10-20 22:00:36 +0200 (Sa, 20 Okt 2012) | 1 line Properly do NR_DEFAULTFLAGS detection/allocation/deallocation ------------------------------------------------------------------------ r22782 | laksen | 2012-10-20 07:44:55 +0200 (Sa, 20 Okt 2012) | 1 line Fixed flags detections code for wide->short optimization code for Thumb-2 ------------------------------------------------------------------------ r22778 | laksen | 2012-10-19 20:23:14 +0200 (Fr, 19 Okt 2012) | 1 line Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc) ------------------------------------------------------------------------ r22647 | laksen | 2012-10-14 21:28:08 +0200 (So, 14 Okt 2012) | 1 line Added register specifications to lpc1768.pp. From Joan Duran ------------------------------------------------------------------------ r22646 | laksen | 2012-10-14 21:10:20 +0200 (So, 14 Okt 2012) | 4 lines Fixed some minor formating issues Implemented a small heap mananger Implemented console IO Changed default LineEnding to CrLf(to ease console IO parsing) ------------------------------------------------------------------------ r22599 | laksen | 2012-10-09 08:58:58 +0200 (Di, 09 Okt 2012) | 1 line Added all STM32F1 configurations ------------------------------------------------------------------------ r22597 | laksen | 2012-10-08 22:10:45 +0200 (Mo, 08 Okt 2012) | 1 line Added initial support for the Cortex-M4F FPv4_S16 FPU ------------------------------------------------------------------------ r22596 | laksen | 2012-10-08 22:04:14 +0200 (Mo, 08 Okt 2012) | 1 line Added FPv4_d16 FPU instructions, and a few extra registers ------------------------------------------------------------------------ r22592 | laksen | 2012-10-08 16:07:40 +0200 (Mo, 08 Okt 2012) | 2 lines Added support for IT block merging Added a peephole pattern check for UXTB->UXTH chains ------------------------------------------------------------------------ r22590 | laksen | 2012-10-08 14:30:00 +0200 (Mo, 08 Okt 2012) | 3 lines Add CBNZ/CBZ instructions Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code Added a number of simple size optimizations for common Thumb-2 instructions ------------------------------------------------------------------------ r22582 | laksen | 2012-10-08 06:49:39 +0200 (Mo, 08 Okt 2012) | 3 lines Fix optimizations of Thumb-2 code Fix problem with loading of condition operand for IT instructions Properly split IT blocks when register allocator tries to spill inside a block. ------------------------------------------------------------------------ r22581 | laksen | 2012-10-08 05:15:40 +0200 (Mo, 08 Okt 2012) | 4 lines Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables. Cortex-M3 devices now also share initialization routine to simplify maintenance STM32F10x classes now have specific units which fit the interrupt source names and counts ------------------------------------------------------------------------ r22580 | laksen | 2012-10-08 05:10:44 +0200 (Mo, 08 Okt 2012) | 2 lines Added support for .section, .set, .weak, and .thumb_set directive for GAS assembler reader IFDEF'ed JVM specific assembler directives, to prevent ait_* set to exceed 32 elements ------------------------------------------------------------------------ r22579 | laksen | 2012-10-08 02:10:52 +0200 (Mo, 08 Okt 2012) | 3 lines Remove all traces of the interrupt vector table generation mechanism Clean up cpuinfo tables Fixed ARMv7M bug(BLX <label> doesn't exist on that version) git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22792 3ad0048d-3df7-0310-abae-a5850022a9f2
* * log and id tags removedfpc2005-05-211-7/+0
| | | | git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@42 3ad0048d-3df7-0310-abae-a5850022a9f2
* initial importfpc2005-05-161-0/+87
git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@1 3ad0048d-3df7-0310-abae-a5850022a9f2
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